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PDF ISL6720AARZ Data sheet ( Hoja de datos )
| Número de pieza | ISL6720AARZ | |
| Descripción | 100V Triple Linear Bias Supply | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
August 23, 2007
ISL6720A
FN6487.1
100V Triple Linear Bias Supply
The ISL6720A is a low cost linear regulator for generating a
low voltage bias supply from intermediate distributed
voltages commonly used in telecom and datacom
applications. It produces three separate outputs, an
adjustable 0V to 20V output rated at up to 125mA which can
be back-biased from an external source such as an auxiliary
transformer winding, a 50mA switched regulated output
adjustable between 0V and 15V, and a fixed continuous 5V
output rated at 25mA.
The ISL6720A may be used as a start-up or a continuous
low power regulator. When operating as a start-up regulator,
it is capable of sourcing over 100mA from a 100V source for
short durations. This period of time allows the power supply
to start-up and provide a low voltage alternate power source,
such as the output of a transformer winding, to the VIO
output. This allows the remaining outputs to be operated
from a lower source voltage thereby minimizing power loss.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG.
#
ISL6720AARZ* 67 20AARZ -40 to +105 11 Ld DFN L11.4x4
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• 100V Input Capability
• Adjustable Auxiliary Winding Regulator with 40V
Withstand Capability
• Up to 125mA Combined Output Current on Switched and
Unswitched Outputs
• 250μs Delayed Start (VIO, VSW) after Continuous
(VCONT) Output
• Regulated Switched (VSW) and Unswitched Outputs
(VIO)
• 5V @ 25mA Continuous Output (VCONT)
• 2-Stage Over-Temperature Protection
• Package Compliant with IPC2221A, Creepage and
Clearance Spacing Requirements
• Pb-Free Available (RoHS Compliant)
Applications
• Telecom/Datacom DC/DC Converters
• Low Power Bias Supplies
Pinout
ISL6720A
(11 LD DFN)
TOP VIEW
VPWR 1
VCONT 2
VCOMP 3
GND 4
VSWADJ 5
11 VIO
10 NC
9 VADJ
8 VSW
7 VSWCOMP
6 ENABLE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6720A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application” on page 3. 17 V < VPWR < 100V, CVSW = CVCONT = 1µF, IVCONT = -250μA,
IVSW = -500μA, VSW Enabled, TA = -40°C to +105°C (Note 4), Typical values are at TA = +25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Current Limit
VPWR = 17V, 48V
VADJ = 15V, VSW Disabled
-225
-380
-500
mA
Maximum External Bias
Load Capacitance Range
VPWR = 17V, 100V
VADJ = 0V, VSWADJ = 0V,
VSW Enabled
IVIO ≤ 1.00mA
(Notes 5, 6)
0.1
40 V
µF
VADJ Bias Current
VPWR = 100V, VSW Disabled
VADJ = 0V, 40V
-75 -25 1 µA
OUTPUT VOLTAGE VSW
Load Capacitance Range
(Note 5)
0.47 1.0 1.5 µF
Compensation Capacitance
(Note 5)
180 220 260
pF
Overall Accuracy
VPWR = 48V
IVSW = -500μA to -50mA
VADJ = 0V, VIO = 22V, 40V ext.
VSWADJ = 0.471V
-5
+5 %
VSWADJ = 1.000V
-3
+3 %
VSWADJ = 2.143V
-3
+3 %
Setpoint Range
VPWR = 48V, VADJ = 0V,
VIO = 40V ext.
VSWADJ = 0V
0 1.5 V
VSWADJ = 2.25V
15
V
Source Voltage Headroom, VIO - VSW
VPWR = 21V, VADJ = 0V,
VSW = 15V, IVSW = -50mA
VIO - VSW
VSW final = 0.95 x VSW initial
1.0 1.5
V
Source Voltage Headroom, VPWR - VSW
VIO = 17 V ext., VADJ = 0V,
VSW = 15V, IVSW = -50mA
VPWR - VSW
VSW final = 0.95 x VSW initial
5.5 V
Minimum Required Load
-500
µA
VSWADJ Discharge Device, VOL
VPWR = 48V, IVSWADJ = 10mA
VSW Disabled, VADJ = 15V
0.10 0.25
V
Maximum VOUT, Faulted VSWADJ
VSWADJ = 4V, VIO = 40V,
IVSW = -50mA
15.1
23 V
VSWADJ DC Gain
VSW = VADJ*GVSWADJ
7 V/V
Long Term Stability
TA = +125°C, 1000 hours, (Note 5) 0.3 %
VPWR = 48V, VSWADJ = 1.0V,
IVSW = -50mA, VADJ = 0V,
VIO = 40V ext.
Operational Current (source)
VPWR = 48V, VADJ = 0V
VIO = 17V ext., VSWADJ = 2.14V
-50
mA
Current Limit
VPWR = 100V, VADJ = 0V
VIO = 40V ext.
-80
-225
-300
mA
VSWADJ Bias Current
VPWR = 100V, VIO = 40V ext.
VSWADJ = 0V, 5V
-1.0
1.0 μA
OUTPUT VOLTAGE VCONT
Overall Accuracy
VPWR = 17V, 100V
IVCONT = -250μA to -25mA
VADJ = 0V, VIO = 10V, 40V ext.
TA = -40 to +105°C
4.925
5.000
5.075
V
5 FN6487.1
August 23, 2007
5 Page 
Package Outline Drawing
L11.4x4
11 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 6/07
4.00
6
PIN 1
INDEX AREA
A
B
ISL6720A
PIN #1 INDEX AREA
6
2X 2.5
8X 0.50
1.0
1
5
11X 0 . 45 ± 0 . 1
4.00 1.58
(4X) 0.15
( 3.75 )
TOP VIEW
( 2.80 )
11
2.80
BOTTOM VIEW
( 11 X 0.65 )
0 .9 ± 0.1mm
( 1.58 )
SIDE VIEW
0 . 2 REF
C
6 0.10 M C A B
0.05 M C
4 0.25
SEE DETAIL "X"
0.10 C
BASE PLANE C
SEATING PLANE
0.08 C
(8X 0.5)
( 11 X 0 . 25 )
TYPICAL RECOMMENDED LAND PATTERN
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
11 FN6487.1
August 23, 2007
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| PDF Descargar | [ Datasheet ISL6720AARZ.PDF ] | |
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