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ISL6455 の電気的特性と機能

ISL6455のメーカーはIntersil Corporationです、この部品の機能は「Triple Output Regulator」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6455
部品説明 Triple Output Regulator
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL6455 Datasheet, ISL6455 PDF,ピン配置, 機能
®
Data Sheet
ISL6455, ISL6455A
December 21, 2005
FN9196.0
Triple Output Regulator with Single
Synchronous Buck and Dual LDO
The ISL6455 is a highly integrated triple output regulator
which provides a single chip solution for FPGAs and wireless
chipset power management. The device integrates a high
efficiency synchronous buck regulator (adjustable) with two
ultra low noise LDO regulators (adjustable). Either the
ISL6455 or ISL6455A can be selected based on whether
3.3V ±10% or 5V ±10% is required as an input voltage.
The synchronous current mode control PWM regulator with
integrated N- and P-channel power MOSFET provides
adjustable voltages based on external resistor setting.
Synchronous rectification with internal MOSFETs is used to
achieve higher efficiency and reduced number of external
components. Operating frequency is typically 750kHz
allowing the use of smaller inductor and capacitor values.
The device can be synchronized to an external clock signal
in the range of 500kHz to 1MHz. The PG_PWM output
indicates loss of regulation on PWM output.
The ISL6455 also has two LDO adjustable regulators using
internal PMOS transistors as pass devices. LDO2 features
ultra low noise typically below 30µVRMS to aid VCO stability.
The EN_LDO pin controls LDO1 and LDO2 outputs. The
ISL6455 also integrates a RESET function, which eliminates
the need for additional RESET IC required in WLAN and
other applications. The IC asserts a RESET signal whenever
the VIN supply voltage drops below a preset threshold,
keeping it asserted for at least 25ms after VIN has risen
above the reset threshold. The PG_LDO output indicates
loss of regulation on either of the two LDO outputs. Other
features include overcurrent protection and thermal
shutdown for all the three outputs.
High integration and the thin Quad Flat No-lead (QFN)
package makes ISL6455 an ideal choice for powering
FPGAs and small form factor wireless cards such as
PCMCIA, mini-PCI and Cardbus-32.
Ordering Information
PART NUMBER* PART
TEMP. PACKAGE PKG.
(Note)
MARKING RANGE (°C) (Pb-Free) DWG. #
ISL6455IRZ
6455IRZ
-40 to 85 24 Ld QFN L24.4x4B
ISL6455AIRZ 6455AIRZ -40 to 85 24 Ld QFN L24.4x4B
Add “-TK” or T5K suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Fully integrated synchronous buck regulator + dual LDO
• PWM output voltage adjustable.
- 0.8V to 2.5V with ISL6455 (VIN = 3.3V)
- 0.8V to 3.3V with ISL6455A (VIN = 5.0V)
• High output current. . . . . . . . . . . . . . . . . . . . . . . . . 600mA
• Dual LDO adjustable options
- LDO1, 1.2V to Vin-0.3V (3.3Vmax). . . . . . . . . . . 300mA
- LDO2, 1.2V to Vin-0.3V (3.3Vmax). . . . . . . . . . . 300mA
• Ultra-compact DC/DC converter design
• Stable with small ceramic output capacitors and no load
• High conversion efficiency
• Low shutdown supply current
• Low dropout voltage for LDOs
- LDO1 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA
- LDO2 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA
• Low output voltage noise
- <30µVRMS (typical) for LDO2 (VCO supply)
• PG_LDO and PG_PWM (PWM and LDO) outputs
• Extensive circuit protection and monitoring features
- PWM overvoltage protection
- Overcurrent protection
- Shutdown
- Thermal shutdown
• Integrated RESET output for microprocessor reset
• Proven reference design for total WLAN system solution
• QFN package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale package footprint Improves PCB
efficiency and is thinner in Profile
• Pb-free plus anneal available (RoHS compliant)
Applications
• WLAN cards
- PCMCIA, Cardbus32, MiniPCI cards
- Compact flash cards
• Hand-held instruments
Related Literature
• TB363 - Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)
• TB389 - PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6455 pdf, ピン配列
Functional Block Diagram
ISL6455, ISL6455A
10nF
3.3V
10k
CT
RESET
PG_LDO
RESET
POR POR
BAND
GAP
REF
1.2V
WINDOW
COMP.
Gm
EN_LDO
GND_LDO
EN
CONTROL
LOGIC
THERMAL
SHUTDOWN
150°C
Gm
WINDOW
COMP.
VIN
RTN
VIN
SGND
FB_PWM
SOFT-
START
SLOPE
COMPENSATION
EA GM
EN
PWM
OVERCURRENT,
OVERVOLTAGE
LOGIC
COMPENSATION
CURRENT
SENSE
GATE
DRIVE
3.3V
750kHz
OSCILLATOR
EN
POWER GOOD
PWM
VOUT
UVLO
SYNC EN
10k 10k
PWM
REFERENCE
0.45V
3.3V
10k
PG_PWM
+-
LDO1
+-
LDO2
VIN_LDO
VIN_LDO
VIN_LDO
VOUT1
VOUT1
FB_LDO1
Rc
Rd
0
10µF
CC1
CC2
33nF
33nF
VOUT2
VOUT2
FB_LDO2
Ra
0
10µF
PVCC
3.3V
Rb
8.2µH
LX VOUT
10µF
PGND
Re
GND
Rf
VOUT
3 FN9196.0
December 21, 2005


3Pages


ISL6455 電子部品, 半導体
ISL6455, ISL6455A
Electrical Specifications
PARAMETER
Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V for ISL6455 and
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = -40°C to 85° (Note 2), typical
values are at TA = 25°C. (Continued)
TEST CONDITIONS
MIN TYP MAX UNITS
ENABLE (EN and (EN_LDO)
EN High Level Input Voltage
As % of VIN
70 -
-%
EN Low Level Input Voltage
As % of VIN
- - 30 %
RESET BLOCK SPECIFICATIONS
RESET (reset released)
RESET (reset asserted)
ISL6455, ISOURCE = 500µA, VIN = 2.90V
ISL6455, ISINK = 1.2mA, VIN = 2.50V
0.8 x
-
-V
VCC
- - 0.3 V
RESET Rising Threshold
ISL6455
2.71 2.77 2.84
V
RESET Falling Threshold
ISL6455
2.69 2.75 2.81
V
RESET (reset released)
RESET (reset asserted)
ISL6455A, ISOURCE = 800µA, VIN = 4.70V
ISL6455A, ISINK = 3.2mA, VIN = 4.10V
0.8 x
-
-V
VCC
- - 0.4 V
RESET Rising Threshold
ISL6455A
4.19 4.27 4.35
V
RESET Falling Threshold
ISL6455A
4.16 4.24 4.32
V
RESET Threshold Hysteresis
ISL6455
- 20 - mV
RESET Threshold Hysteresis
ISL6455A
- 30 - mV
RESET Active Timeout Period (Note 5)
POWER GOOD (PG_LDO)
CT = 0.01µF
- 25 - ms
Minimum Input Voltage for Valid PG_LDO
- 1.2 -
V
PGOOD Threshold (Rising)
PGOOD Threshold (Falling)
FB_LDO vs 1.184V Vref
+11 +15 +17
-17 -15 -11
%
%
PGOOD Output Voltage Low
PGOOD Output Leakage Current
IOL = 1.2mA
PG_LDO = GND or VIN
- - 0.4 V
- 0.01 0.1 µA
PWM OUTPUT OVERVOLTAGE
Overvoltage Threshold
FB_PWM vs 0.45V Vref
28 31 34 %
NOTES:
3. Specifications at -40°C and +85°C are guaranteed by 25°C test with margin limits.
4. This is the VIN current consumed when the device is active but not switching. Does not include gate drive current.
5. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V.
6. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01µF) the RESET time is 25ms; at 1000nF (0.1µF) the
RESET time would be 250ms.
7. Guaranteed by design, not production tested.
8. Add the external feedback resistor mismatch error to get initial VOUT accuracy.
6 FN9196.0
December 21, 2005

6 Page



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共有リンク

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部品番号部品説明メーカ
ISL6455

Triple Output Regulator

Intersil Corporation
Intersil Corporation
ISL6455A

Triple Output Regulator

Intersil Corporation
Intersil Corporation
ISL6455AIRZ

Triple Output Regulator

Intersil Corporation
Intersil Corporation
ISL6455IRZ

Triple Output Regulator

Intersil Corporation
Intersil Corporation


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