|
|
PDF ISL6263B Data sheet ( Hoja de datos )
| Número de pieza | ISL6263B | |
| Descripción | 5-Bit VID Single-Phase Voltage Regulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL6263B (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
®
Data Sheet
July 8, 2010
ISL6263B
FN6388.3
5-Bit VID Single-Phase Voltage Regulator
with Current Monitor for IMVP-6+ Santa
Rosa GPU Core
The ISL6263B IC is a Single-Phase Synchronous-Buck
PWM voltage regulator featuring Intersil’s Robust Ripple
Regulator (R3) Technology™. The ISL6263B is an
implementation of the Intel® Mobile Voltage Positioning
(IMVP) protocol for GPU Render Engine core power.
Integrated current monitor, droop amplifier, MOSFET drivers
and bootstrap diode result in smaller implementation area and
lower component cost.
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency PWM and hysteretic PWM, delivering
excellent light-load efficiency and superior load transient
response by commanding variable switching frequency
during the transitory event. For maximum conversion
efficiency, the ISL6263B automatically enters diode-
emulation mode (DEM) should the inductor current attempt
to flow negative. DEM is highly configurable and easy to
set-up. A PWM filter can be enabled that prevents the
switching frequency from entering the audible spectrum as a
result of extremely light load while in DEM.
The Render core voltage can be dynamically programmed
from 0.41200V to 1.28750V by the five VID input pins
without requiring sequential stepping of the VID states. The
ISL6263B requires only one capacitor for both the soft-start
slew-rate and the dynamic VID slew-rate by internally
connecting the SOFT pin to the appropriate current source.
Processor socket Kelvin sensing is accomplished with an
integrated unity-gain true differential amplifier.
Ordering Information
PART NUMBER
PART
PACKAGE PKG.
(Notes 2, 3)
MARKING TEMP (°C) (Pb-Free) DWG. #
ISL6263BHRZ ISL6263 BHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5
ISL6263BHRZ-T ISL6263 BHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5
(Note 1)
Tape and Reel
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL6263B. For more information on MSL please see techbrief
TB363.
Features
• Precision single-phase core voltage regulator
- 0.5% system accuracy 0°C to +100°C
- Differential remote GPU die voltage sensing
- Differential droop voltage sensing
• Real-time GPU current monitor output
• Applications up to 25A
• Input voltage range: +5.0V to +25.0V
• Programmable PWM frequency: 200kHz to 500kHz
• Pre-biased output start-up capability
• 5-bit voltage identification input (VID)
- 1.28750V to 0.41200V
- 25.75mV steps
- Sequential or non-sequential VID change on-the-fly
• Configurable PWM modes
- forced continuous conduction mode
- automatic entry and exit of diode emulation mode
- selectable audible frequency PWM filter
• Integrated MOSFET drivers and bootstrap diode
• Choice of current sensing schemes
- Lossless inductor DCR current sensing
- Precision resistive current sensing
• Overvoltage, undervoltage and overcurrent protection
• Pb-free (RoHS compliant)
Pinout
ISL6263B (32 LD 5x5 QFN)
TOP VIEW
RBIAS 1
32 31
30 29 28 27
26 25
24 VID1
SOFT 2
23 VID0
OCSET 3
22 PVCC
VW 4
COMP 5
THERMAL PAD
(BOTTOM)
21 LGATE
20 PGND
FB 6
19 PHASE
VDIFF 7
18 UGATE
VSEN 8
17 BOOT
9 10 11 12 13 14 15 16
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2008, 2010. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6263B
Absolute Voltage Ratings
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
PHASE to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V
(<100ns Pulse Width, 10μJ) -5.0V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
BOOT to VSS or PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
UGATE. . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V
(<200ns Pulse Width, 20μJ) -4.0V
LGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V
(<100ns Pulse Width, 4μJ) -2.0V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . -0.3V to VSS, VDD +0.3V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5) θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
35
6
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . -10°C to +100°C
VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +25V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
FDE to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
These specifications apply for TA = -10°C to +100°C, unless otherwise stated. All typical specifications
TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range,
-10°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
VIN
VIN Input Resistance
VIN Shutdown Current
VDD and PVCC
R VIN
IVIN_SHDN
VR_ON = 3.3V
VR_ON = 0V, VIN = 25V
1.0 MΩ
1.0 µA
VDD Input Bias Current
VDD Shutdown Current
VDD POR THRESHOLD
Rising VDD POR Threshold Voltage
Falling VDD POR Threshold Voltage
REGULATION
Output Voltage Range
VID Voltage Step
IVDD
IVDD_SHDN
VR_ON = 3.3V
VR_ON = 0V, VDD = 5.0V
2.7 3.3 mA
1.0 µA
VVDD_THR
VVDD_THF
4.35 4.50
3.85 4.10
V
V
VGFX_MAX
VGFX_MIN
VID<4:0> = 00000
VID<4:0> = 11111
VID<4:0> = 00000 to 11110 (1.28750V
to 0.51500V)
1.28750
0.41200
25.75
V
V
mV/step
VID<4:0> = 11110 to 11111 (0.51500V to
0.41200V)
103
mV
System Accuracy
VID = 1.28750V to 0.74675V
TA = 0°C to +100°C
VID = 0.72100V to 0.51500V
TA = 0°C to +100°C
VID = 0.41200
TA = 0°C to +100°C
-0.5
-1.0
-3.0
0.5 %
1.0 %
3.0 %
5 FN6388.3
July 8, 2010
5 Page 
ISL6263B
+
Σ
+
VDIFF
VDD
−
OCP
+
+
−
10µA ↓
OCSET
+
DROOP
−
VSUM
DFB
DROOP
VO
VSEN
+
RTN
−
ROCSET
PHASE
RS
CFILTER1
RFILTER1
RFILTER2
CFILTER2
CFILTER3
LOUT
DCR
COUT
ESR
VCC_SNS
TO
PROCESSOR
SOCKET
VSS_SNS
KELVIN
CONNECTIONS
FIGURE 5. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH GPU SOCKET KELVIN SENSING AND INDUCTOR DCR CURRENT SENSING
Smooth mode transitions are facilitated by the R3 modulator
which correctly maintains the internally synthesized ripple
current information throughout mode transitions.
Current Monitor
The ISL6263B features a current monitor output. The
voltage between the IMON and VSS pins is proportional to
the output inductor current. The output inductor current is
proportional to the voltage between the DROOP and VO
pins. The IMON pin has source and sink capability for close
tracking of transient current events. The current monitor
output is expressed in Equation 1:
VIMON = (VDROOP – VO) ⋅ 31
(EQ. 1)
Protection
The ISL6263B provides overcurrent protection (OCP),
overvoltage protection (OVP), and undervoltage protection
(UVP) as shown in Table 3.
Overcurrent protection is tied to the voltage droop, which is
determined by the resistors selected in the Static Droop
Design Using DCR Sensing section. After the load line is set,
the OCSET resistor can be selected. The OCP threshold
detector is checked every 15µs and will increment a counter
if the OCP threshold is exceeded, conversely the counter will
be decremented if the load current is below the OCP
threshold. The counter will latch an OCP fault when the
counter reaches eight. The fastest OCP response for
overcurrent levels that are no more than 2.5x the OCP
threshold is 120µs, which is eight counts at 15µs each. The
ISL6263B protects against hard shorts by latching an OCP
fault within 2µs for overcurrent levels exceeding 2.5x the
OCP threshold. The value of ROCSET is calculated in
Equation 2:
ROCSET = -I-O-----C-1---0-⋅--.-R-1----dμ---r-A-o----o---p-
(EQ. 2)
For example: The desired overcurrent trip level, Ioc, is 30A,
Rdroop load-line is 8mΩ, Equation 2 gives ROCSET = 24kΩ.
Undervoltage protection is independent of the overcurrent
protection. If the output voltage measured on the VO pin is
less than +300mV below the voltage on the SOFT pin for
longer than 1ms, the controller will latch a UVP fault. If the
output voltage measured on the VO pin is greater than
195mV above the voltage on the SOFT pin for longer than
1ms, the controller will latch an OVP fault. Keep in mind that
VSOFT will equal the voltage level commanded by the VID
states only after the soft-start capacitor CSOFT has slewed to
the VID DAC output voltage. The UVP and OVP detection
circuits act on static and dynamic VSOFT voltage.
When an OCP, OVP, or UVP fault has been latched, PGOOD
becomes a low impedance and the gate driver outputs
UGATE and LGATE are pulled low. The energy stored in the
inductor is dissipated as current flows through the low-side
MOSFET body diode. The controller will remain latched in
the fault state until the VR_ON pin has been pulled below the
falling VR_ON threshold voltage VVR_ONL or until VDD has
gone below the falling POR threshold voltage VVDD_THF.
A severe-overvoltage protection fault occurs immediately
after the voltage between the VO and VSS pins exceed the
rising severe-overvoltage threshold VOVPS which is 1.545V,
the same reference voltage used by the VID DAC. The
11 FN6388.3
July 8, 2010
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ISL6263B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL6263 | 5-Bit VID Single-Phase Voltage Regulator | Intersil Corporation |
| ISL6263B | 5-Bit VID Single-Phase Voltage Regulator | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |