|
|
PDF ISL6172DRZA Data sheet ( Hoja de datos )
| Número de pieza | ISL6172DRZA | |
| Descripción | Dual Low Voltage Hot Swap Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL6172DRZA (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
®
Data Sheet
June 2004
ISL6172
FN9158
Dual Low Voltage Hot Swap Controller
This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V bias supply voltage range with a second lower
voltage rail down to less than 1V. It features a charge pump for
driving external N-Channel MOSFETs, regulated current
protection and duration, output undervoltage monitoring and
reporting, optional latch-off or retry response, and adjustable
soft-start.
The current regulation level (CR) for each rail is set by two
external resistors and each CR duration is set by an external
capacitor on the TIM pin. After the CR duration has expired
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s). The ISL6172 offers a
latched output or indefinite auto retry mode of operation.
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6172DRZA * 0 to +85 28 Ld 5x5 QFN (Pb-free) L28.5x5
ISL6172DRZA-T * 0 to +85 28 Ld 5x5 QFN (Pb-free) L28.5x5
ISL6172EVAL3 Evaluation Platform
* Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J Std-020B.
Pinout
28 LEAD QFN
TOP VIEW
Features
• Dual Supply Hot Swap Power Distribution Control to <1V
• Less than 1µs Response Time to Dead Short
• Overcurrent Circuit Breaker Fault Isolation and
Programmable Current Regulation Level Protection
Functions
• Programmable Current Regulation Duration
• Charge Pump Allows the use of N-Channel MOSFETs
• Rail Independent Control, Monitoring and Reporting I/O
• Adjustable Ramp up for Inrush Protection During Turn On
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Latch-off or Auto Reset Response to Fault Functions
• Adjustable Current Regulation Threshold as low as 20mV
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-free
Applications
• Power Supply Sequencing, Distribution and Control
• Hot Swap/Electronic Breaker Circuits
• Network Hubs, Routers, Switches
• Hot Swap Bays, Cards and Modules
V1(in)
Rsns1
V1(out)
28 27 26 25 24 23 22
SNS2 1
21 SNS2
VO1 2
20 VO2
SS1 3
19 SS2
GT1 4
18 GT2
FLT1 5
17 FLT2
PG1 6
16 PG2
CT1 7
15 CT2
8 9 10 11 12 13 14
EN1 EN2
RTR/LTCH
BIAS
CPQ+
VS1
SNS1 GT1 VO1
UV1
PG1
FLT1
SS1
CPQ-
CPVDD
ISL6172
OCREF
SS2
FLT2
PGND
PG2
GND
UV2
CT1 CT2 VS2 SNS2 GT2 VO2
V2(in)
Rsns2
FIGURE 1. TYPICAL APPLICATION
V2(OUT)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6172
Absolute Maximum Ratings
VBIAS/VIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +12V
ENx, RTR/LTCH, SNSx, PGx, FLTx, VSx, CTx, UVx,
SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC
Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .1kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . .75V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . . 1.5kV
Thermal Information
Thermal Resistance (Typical, Notes 1, 4) θJA (°C/W) θJC (°C/W)
5x5 QFN Package . . . . . . . . . . . . . . . .
42
12.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
For recommended soldering conditions, see Tech Brief TB389.
(QFN - Leads Only)
Operating Conditions
VBIAS/VIN1 Supply Voltage Range. . . . . . . . . . . . +2.25V to +3.63V
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. All voltages are relative to GND, unless otherwise specified.
3. 1V (min) on the BIAS pin required for FLT to be valid.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = 2.5V to +3.3V, TA = TJ = 0°C - 85°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
CURRENT REGULATION CONTROL
Current Regulation Threshold Voltage
Current Regulation Accuracy
Current Regulation Threshold Voltage
Current Regulation Accuracy
CT Threshold Voltage
CT Charging Current
GATE DRIVE
VCRVTH_1
VCRVTH_1R
VCRVTH_2
VCRVTH_2R
VCT_Vth
ICT
RISET = 1.25K 1%, ISET = 20µA
RISET = 1.25K 1%, ISET = 20µA
RISET = 2.50K 1%, ISET = 20µA
RISET = 2.50K 1%, ISET = 20µA
20
-20
45
-10
1.156
GATE Response Time from WOC (Open)
pd_woc_open
GATE open
100mV of overdrive on the WOC
comparator
GATE Response Time from WOC (Loaded) pd_woc_load GATE = 1nF
GATE Response Time in Current Regulation
mode (Loaded)
pd_cr_load
GATE = 1nF
120% Load Current
GATE Response Time in “Quick-Slew” pull-
down Mode (Loaded)
pd_oc_load
GATE = 1nF
22mV of overdrive on Amplifier
Input
GATE Turn-On Current
Current Limit Amplifier Transconductance
GATE Pull Down Resistor (WOC, fault or off
conditions)
IGATE
Gm
Ig_woc
GATE = 2V
VVS = 2V
VSNS = 2.1V
VVS - VSNS1 = -25mV
TJ = 25°C
Gate = 2V
14
18
GATE Pull Down Resistor (“Quick-Slew”
mode)
Ig_qs
TJ = 25°C
Gate = 2V
9
TYP
25
50
1.178
10
3
80
4
50
18.5
0.35
25
11
MAX
UNIT
30
+20
55
+10
1.200
mV
%
mV
%
V
µA
ns
ns
ms
µs
22 µA
ms
42 Ω
13 kΩ
5
5 Page 
ISL6172
Tracking
CH1: VO1, CH2: VO2, T = 2ms/DIV, CSS = 0.066µF
FIGURE 17. TRACKING MODE WAVEFORMS
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor. In addition, their EN pins also must be tied
together. Typical Start-up waveforms in this mode are shown
in Figure 17 above. If one channel goes down for any
reason, the other one will too. One important thing to note
here is that only the overcurrent latch-off mode will work.
Autoretry feature WILL NOT work. Retry must be controlled
manually through EN.
TYPICAL HOT-PLUG POWER UP SEQUENCE
1. When power is applied to the IC on BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher the IC comes out of
POR. Both SS and CT caps remain discharged and the
gate (GT) voltage remains low.
3. ENx pin, when pulled low (below it’s specified threshold),
enables the respective channel.
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
same rate as the SS cap voltage. This is tightly controlled
by the Soft-start amplifier shown in the block diagram.
5. CTx cap begins to charge at the same time as the
corresponding SS cap.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise
7. If the output voltage reaches its full value before the
corresponding CTx cap voltage reaches 1.178V, the
latter gets discharged and the FLT remains deasserted.
Else, the channel shuts down and FLT is asserted.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, Power Good (PG) output goes active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or CT timer is not timed out. The latter indicates
expiration of current regulation duration.
State Diagram
This is shown in Figure 18. It provides a quick overview of
the IC operation and can also be used as a troubleshooting
road map.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL6172DRZA.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL6172DRZA | Dual Low Voltage Hot Swap Controller | Intersil Corporation |
| ISL6172DRZA-T | Dual Low Voltage Hot Swap Controller | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |