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PDF HIP2120 Data sheet ( Hoja de datos )
| Número de pieza | HIP2120 | |
| Descripción | High Frequency Half-Bridge Drivers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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100V, 2A Peak, High Frequency Half-Bridge Drivers with
Adjustable Dead Time Control and PWM Input
HIP2120, HIP2121
The HIP2120 and HIP2121 are 100V, high frequency, half-bridge
MOSFET driver ICs. They are based on the popular ISL2100A and
ISL2101A half-bridge drivers.
These drivers have a programmable dead-time to insure
break-before-make operation between the high-side and low-side
drivers. The dead-time is adjustable up to 250ns.
A single PWM logic input controls both bridge outputs (HO, LO). An
enable pin (EN), when low, drives both outputs to a low state. All
logic inputs are VDD tolerant and the HIP2120 has CMOS inputs
with hysteresis for superior operation in noisy environments.
The HIP2120 has hysteretic inputs with thresholds that are
proportional to VDD. The HIP2121 has 3.3V logic/TTL compatible
inputs.
Two package options are provided. The 10 Ld 4x4 DFN package has
standard pinouts. The 9 Ld 4x4 DFN package omits pin 2 to comply
with 100V conductor spacing per IPC-2221.
Features
• 9 Ld TDFN “B” Package Compliant with 100V Conductor
Spacing Guidelines per IPC-2221
• Break-Before-Make Dead-Time Prevents Shoot-through and is
adjustable up to 220ns
• Bootstrap Supply Max Voltage to 114VDC
• Wide Supply Voltage Range (8V to 14V)
• Supply Undervoltage Protection
• CMOS Compatible Input Thresholds with Hysteresis (HIP2120)
• 1.6Ω/1Ω Typical Output Pull-up/Pull-down Resistance
• On-Chip 1Ω Bootstrap Diode
Applications
• Telecom Half-Bridge DC/DC Converters
• UPS and Inverters
• Motor Drives
• Class-D Amplifiers
• Forward Converter with Active Clamp
Related Literature
• FN7670 “HIP2122, HIP2123 100V, 2A Peak, High Frequency
Half-Bridge Driver with Delay Timers”
HALF BRIDGE
HIP2120/21
VDD
HB
PWM
CONTROLLER
PWM
EN
RDT
HO
HS
VSS
EPAD
LO
100V max
SECONDARY
CIRCUITS
FEEDBACK
WITH
ISOLATION
FIGURE 1. TYPICAL APPLICATION
200
160
140
120
100
80
60
40
20
8 16 24 32 40 48 56 64
RDT (kΩ)
FIGURE 2. DEAD-TIME vs TIMING RESISTOR
80
December 23, 2011
FN7668.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
HIP2120, HIP2121
Absolute Maximum Ratings
Supply Voltage, VDD, VHB - VHS (Notes 5, 6) . . . . . . . . . . . . . . . -0.3V to 18V
PWM and EN Input Voltage (Note 6) . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Maximum Recommended Operating
Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS + 8V to VHS + 14V and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - 1V to VDD + 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . .
42
4
9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . .
42
4
Max Power Dissipation at +25°C in Free Air
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
9 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E). . . . . . . . . . 3000V
Machine Model Class B (Tested per JESD22-A115-A). . . . . . . . . . . . . . 300V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. The HIP2120 and HIP2121 are capable of derated operation at supply voltages exceeding 14V. Figure 20 shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to VSS unless otherwise specified.
7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0K, PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
TA = +25°C
TA = -40°C to +125°C
MIN TYP MAX MIN (Note 9) MAX (Note 9) UNITS
SUPPLY CURRENTS
VDD Quiescent Current
VDD Operating Current
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
INPUT PINS
IDD80
IDD8k
IDDO80k
IDDO8k
IHB
IHBO
IHBS
IHBSO
RDT = 80k
RDT = 8k
f = 500kHz, RDT = 80k
f = 500kHz, RDT = 8k
LI = HI = 0V
f = 500kHz
LI = HI = 0V; VHB = VHS = 114V
f = 500kHz; VHB = VHS = 114V
- 470 850
- 1.0 2.1
- 2.5 3
- 3.4 4
- 65 115
- 2.0 2.5
- 0.05 1.5
- 1.2 1.5
-
-
-
-
-
-
-
-
900 µA
2.2 mA
3 mA
4 mA
150 µA
3 mA
10 µA
1.6 mA
Low Level Input Voltage
Threshold
VIL HIP2120 (CMOS)
3.7 4.4 -
2.7
-V
Low Level Input Voltage
Threshold
VIL HIP2121 (3.3V/TTL)
1.4 1.8 -
1.2
-V
High Level Input Voltage
Threshold
VIH HIP2120 (CMOS)
- 6.54 7.93
5.3
8.2 V
High Level Input Voltage
Threshold
VIH HIP2121 ((3.3V/TTL)
- 1.8 2.2
-
2.4 V
5 FN7668.0
December 23, 2011
5 Page 
HIP2120, HIP2121
Functional Description
Functional Overview
When connected to a half bridge, the output of the bridge on the
HS node follows the PWM input. In other words, when the PWM
input is high, the high-side bridge FET is turned on and the
low-side FET is off. When the PWM input is low, the low-side
bridge FET is turned on and the high-side is turned off. The
enable pin (EN), when low, drives both outputs to a low state.
When the PWM input transitions high or low, it is necessary to
insure that both bridge FETS are not on at the same time to
prevent shoot-through currents (break before make). The internal
programmable timers delay the rising edge of either output
resulting with both outputs being off before either of the bridge
FETs is driven on. An 8kΩ resistor connected between RDT and
VSS results in a nominal dead time of 220ns. An 80kΩ results
with a minimum nominal dead time of 25ns. Resistors values
less than 8k and greater than 80k are not recommended.
The high-side driver bias is established by the boot capacitor
connected between HB and HS. The charge on the boot capacitor
is provided by the internal boot diode that is connected to VDD.
The current path to charge the boot capacitor occurs when the
low-side bridge FET is on. This charge current is limited in
amplitude by the inherent resistance of the boot diode and by the
drain-source voltage of the low-side FET. Assuming that the on
time of the low-side FET is sufficiently long to fully charge the
boot capacitor, the boot voltage will charge very close to VDD
(less the boot diode drop and the low-side FET on voltage).
When the PWM input transitions high, the high-side bridge FET is
driven on after the dead time. Because the HS node is connected
to the source of the high-side FET, the HS node will rise almost to
the level of the bridge voltage (less the conduction voltage across
the bridge FET). Because the boot capacitor voltage is referenced
to the source voltage of the high-side FET, the HB node is VDD
volts above the HS node and the boot diode is reversed biased.
Because the high-side driver circuit is referenced to the HS node,
the HO output is now approximately VHB + VBRIDGE above
ground.
During the low to high transition of the HS node, the boot
capacitor sources the necessary gate charge to fully enhance the
high-side bridge FET gate. After the gate is fully charged, the boot
capacitor no longer sources the charge to the gate but continues
to provide bias current to the high-side driver. It is clear that the
charge of the boot capacitor must be substantially larger than
the required charge of the high-side FET and high-side driver
otherwise the boot voltage will sag excessively. If the boot
capacitor value is too small for the required maximum of on-time
of the high-side FET, the high-side UV lockout may engage
resulting with an unexpected operation.
Application Information
Selecting the Boot Capacitor Value
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is about 20 times the
gate charge of the driven power FET for approximately a 5% drop
in voltage after the charge has been transferred from the boot
capacitor to the gate capacitance.
The following parameters are required to calculate the value of
the boot capacitor for a specific amount of voltage droop. In this
example, the values used are arbitrary. They should be changed
to comply with the actual application.
VDD = 10V
VHB = VDD - 0.6V
= VHO
Period = 1ms
IHB = 100µA
RGS = 100kΩ
Ripple= 5%
Igate_leak = 100nA
Qgate80V = 64nC
VDD can be any value between 7 and 14VDC
High side driver bias voltage (VDD - boot diode
voltage) referenced to VHS
This is the longest expected switching period
Worst case high side driver current when
xHO = high
(this value is specified for VDD = 12V but the
error is not significant)
Gate-source resistor
(usually not needed)
Desired ripple voltage on the boot cap (larger
ripple is not recommended)
From the FET vendor’s datasheet
From Figure 21
12
ID = 33A
10
VDS = 80V
VDS = 50V
8 VDS = 20V
6
4
2
0
0 10 20 30 40 50 60 70 80
QG TOTAL GATE CHARGE (nC)
FIGURE 21. TYPICAL GATE CHARGE OF A POWER FET
The following equations calculate the total charge required for
the Period. This equation assumes that all of the parameters are
constant during the period duration. The error is insignificant if
the ripple is small.
Qc = Qgate80V + Period x (IHB + VHO/RGS + Igate_leak)
Cboot = Qc/(Ripple * VDD)
Cboot = 0.52µF
If the gate to source resistor is removed (RGS is usually not needed
or recommended), then:
Cboot = 0.33µF
11 FN7668.0
December 23, 2011
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HIP2120.PDF ] | |
Hoja de datos destacado
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