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PDF H55S5132EFR-75M Data sheet ( Hoja de datos )
| Número de pieza | H55S5132EFR-75M | |
| Descripción | 512Mbit (16Mx32bit) Mobile SDR Memory | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O
Specification of
512M (16Mx32bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 4,194,304 x32
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Sep. 2010
1
1 page  
il;o;nar
512Mbit (16Mx32bit) Mobile SDR Memory
H55S5122EFR Series / H55S5132EFR Series
FEATURES
● Standard SDRAM Protocol
● Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
● MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Programmable burst length: 1, 2, 4, 8 or full page
● Programmable Burst Type: sequential or interleaved
● Programmable CAS latency of 3 or 2
● Programmable Drive Strength
● Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
● Operation Temperature
- Mobile Temp.: -30oC ~ 85oC
● Package Type: 90ball FBGA, 0.8mm pitch, 8 x 13 [mm2], t=1.0mm max, Lead & Halogen Free
512M SDRAM ORDERING INFORMATION
Part Number
H55S5122EFR-60M
H55S5122EFR-75M
H55S5122EFR-A3M
H55S5132EFR-60M
H55S5132EFR-75M
H55S5132EFR-A3M
Clock Frequency
Page
Size
Organization Interface
Package
166MHz
133MHz
105MHz
166MHz
133MHz
105MHz
2KBytes
(Normal)
4banks x 4Mb x 32
1KBytes
(Reduced)
LVCMOS
90 Ball FBGA
Lead & Halogen
Free
Rev 1.2 / Sep. 2010
5
5 Page 
il;o;nar
512Mbit (16Mx32bit) Mobile SDR Memory
H55S5122EFR Series / H55S5132EFR Series
DC CHARACTERISTICS II (TA= -30 to 85oC)
Parameter
Symbol
Test Condition
Speed
Unit Note
166MHz 133MHz 105MHz
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
70
60
50 mA 1
Precharge Standby
Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = 15ns
IDD2PS CKE ≤ VIL(max), tCK = ∞
0.3 mA
0.3 mA
Precharge Standby
Current
in Non Power Down
Mode
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= 15ns
Input signals are changed one time
during 2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
5
1
mA
Active Standby Current IDD3P CKE ≤ VIL(max), tCK = 15ns
in Power Down Mode IDD3PS CKE ≤ VIL(max), tCK = ∞
5
mA
3
Active Standby Current IDD3N
in Non Power Down
Mode
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= 15ns
Input signals are changed one time
during 2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
10
5
mA
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active; 50% data change
each burst transfer
70
60
60 mA 1
Auto Refresh Current IDD5 tRFC ≥ tRFC(min)
100 mA
Self Refresh Current IDD6 CKE ≤ 0.2V
See Next Page
mA 2
Standby Current in
Deep Power Down
Mode
IDD7
CKE ≤ 0.2V
See the pages for the Deep Power
Down operation.
20
uA 3
Notes:
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. See the tables of next page for more specific IDD6 current values.
3. Please contact Hynix office for more information and ability for DPD operation.
Deep Power Down operation is a hynix optional function.
Rev 1.2 / Sep. 2010
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet H55S5132EFR-75M.PDF ] | |
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