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PDF H57V2582GTR-75C Data sheet ( Hoja de datos )
| Número de pieza | H57V2582GTR-75C | |
| Descripción | 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
www.DataSheet4U.com
256M (32Mx8bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 8,388,608 x 8
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Aug. 2009
1
1 page  
111
Synchronous DRAM Memwowrwy.D2ata5S6heMet4bU.ictom
H57V2582GTR Series
54 TSOP II Pin ASSIGNMENTS
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Rev 1.0 / Aug. 2009
54 Pin TSOPII
400mil x 875mil
0.8mm pin pitch
54 VSS
53 DQ7
52 VSSQ
51 NC
50 DQ6
49 VDDQ
48 NC
47 DQ5
46 VSSQ
45 NC
44 DQ4
43 VDDQ
42 NC
41 VSS
40 NC
39 DQM
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
5
5 Page 
111
Synchronous DRAM Memwowryw2.5D6aMtbaitS h e e t 4 U . c o
H57V2582GTR Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Symbol
System Clock Cycle Time
CL = 3
CL = 2
Clock High Pulse Width
Clock Low Pulse Width
Access Time From Clock
CL = 3
CL = 2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in High-Z
Time
CL = 3
CL = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
166
Min Max
6.0 1000
- 1000
2.5 -
2.5 -
- 5.4
--
2.0 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.0 -
2.7 5.4
--
133
Min Max
7.5 1000
10 1000
2.5 -
2.5 -
- 5.4
-6
2.5 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.5 -
0.8 -
1.0 -
2.7 5.4
36
Unit Note
ns
ns
ns 1
ns 1
ns 2
ns 2
ns
ns 1
ns 1
ns 1
ns 1
ns 1
ns 1
ns 1
ns 1
ns
ns
ns
Note:
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added
to the parameter.
Rev 1.0 / Aug. 2009
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet H57V2582GTR-75C.PDF ] | |
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