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AS8C801801 の電気的特性と機能

AS8C801801のメーカーはAlliance Semiconductorです、この部品の機能は「3.3V Synchronous ZBT SRAMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 AS8C801801
部品説明 3.3V Synchronous ZBT SRAMs
メーカ Alliance Semiconductor
ロゴ Alliance Semiconductor ロゴ 




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AS8C801801 Datasheet, AS8C801801 PDF,ピン配置, 機能
256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
3.3V I/O, Burst Counter
Pipelined Outputs
AS8C803601
AS8C801801
Features
256K x 36, 512K x 18 memory configurations
Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (V DDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP).
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read or write.
TheAS8C803601/801801 contain data I/O, address and control signal
registers. Output enable is the only asynchronoussignal and can be
used to disable the outputsat any given time.
A Clock Enable(CEN) pin allows operation of the toAS8C803601/ 801801
be suspended as long as necessary. All synchronousinputs are ignored when
(CEN)is high and the internal device registers will hold their previous values.
There are three chip enable pins (CE1, CE2,CE2) that allow the user
to deselect the device when desired. If anyone of these three are not asserted
when ADV/LD is low, no new memoryoperation can be initiated. However,
any pending data transfers (reads or writes) will be completed. The data bus
will tri-state two cycles after chip is deselected or a write is initiated.
TheAS8C803601/801801 have an on-chip burst counter. In the burst
mode,the AS8C803601/801801 can provide fourcycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADVL/ D =LOW) or increment the internal burst counter
Description
The AS8C803601/801801 are3.3V high-speed 9,437,184 bit
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
(ADV/LD = HIGH).
The AS8C803601/801801 SRAM utilize IDT's latest high-performance
CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP) .
reads. Thus, they have been given the name ZBTMT, or Zero Bus Turnaround.
Pin Description Summary
A0-A18
Address Inputs
CE1, CE2, CE2
OE
R/W
Chip Enables
Output Enable
Read/Write S ignal
CEN Clock Enable
BW1, BW2, BW3, BW4
Individual Byte Write Selects
CLK
ADV/LD
Clock
Advance burst address / Load new address
LBO Linear / In terleaved B urst Order
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core P ower, I/ O Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Asynchronous
Synchronous
Static
Static
5304 tbl 01
SEPTEMBER 2010
1
DSC-5304/07

1 Page





AS8C801801 pdf, ピン配列
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBTFeature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperatur e Ranges
Functional Block Diagram
LBO
Address A [0:18]
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
DQ
DQ
512x18 BIT
MEMORY ARRAY
Address
Control
DI DO
DQ
Clk
Control Logic
Clock
OE
Mux Sel
D
Output Register
Q
Gate
,5304 drw 01
Data I/O [0:15],
I/O P[1:2]
6.342


3Pages


AS8C801801 電子部品, 半導体
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBTFeature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 512K x 18
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial &
Industrial
Unit
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VDD(1)
VDD
VDD(1)
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD(1)
VDD
ZZ
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
5304 drw 02a
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to V DD as long as
the input voltage is VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU= Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied LOW (V SS), or tied HIGH (V DD).
VTERM(2)
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to V DD
V
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
V
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
Commercial
-0 to +70
oC
TA(7) Operating Temperature
Industrial
Operating Temperature
-40 to + 85
oC
TBIAS
Temperature
Under B ias
-55 to + 125
oC
TSTG Storage
Temperature
-55 to + 125
oC
PT
, IOUT
Power Di ssipation
DC Output Cu rrent
2.0 W
50 mA
NOTES:
5304 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V DDQ during power
supply ramp up.
7. During production testing, the case temperature equals T A.
100 TQFP Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max. Unit
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
CIN Input Capacitance
VIN = 3dV
5 pF
CIN Input Capacitance
VIN = 3 dV
CI/O I/O Capacitance
VOUT = 3dV
119 BGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
7 pF
5304 t bl 07
Max. Unit
CI/O I/O Capacitance
VOUT = 3 dV
CIN Input Capacitance
VIN = 3dV
7 pF
CI/O I/O Capacitance
VOUT = 3dV
7 pF
5304 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Max. Unit
TBD pF
TBD pF
5304 t bl 0 7b
6.642

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
AS8C801800

3.3V Synchronous SRAMs

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AS8C801800-QC150N

3.3V Synchronous SRAMs

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AS8C801801

3.3V Synchronous ZBT SRAMs

Alliance Semiconductor
Alliance Semiconductor
AS8C801801-QC150N

3.3V Synchronous ZBT SRAMs

Alliance Semiconductor
Alliance Semiconductor


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