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AS8C401825-QC75N の電気的特性と機能

AS8C401825-QC75NのメーカーはAlliance Semiconductorです、この部品の機能は「3.3V Synchronous SRAMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 AS8C401825-QC75N
部品説明 3.3V Synchronous SRAMs
メーカ Alliance Semiconductor
ロゴ Alliance Semiconductor ロゴ 




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AS8C401825-QC75N Datasheet, AS8C401825-QC75N PDF,ピン配置, 機能
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
AS8C403625
AS8C401825


Features
128K x 36, 256K x 18 memory configurations
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP),
Description
TheAS8C403625/1825 are high-speed SRAMs organized as
128K x 36/256K x 18. The AS8C403625/1825 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to gen-
erate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the AS8C403625/1825 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The AS8C403625/1825 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP)
Pin Description Summary
A0-A17
Address Inputs
CE
CS0, CS1
Chip Enable
Chip Selects
OE Output Enable
GW Global Write Enable
BWE Byte Write Enable
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
CLK Clock
ADV Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO Linear / Interleaved Burst Order
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock
TDO Test Data Output
TRST
JTAG Reset (Optional)
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
NOTE:
1. BW3 and BW4 are not applicable for the AS8C401825.
.
1
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
N/A
5280 tbl 01
SEPTEMBER 2010
DSC-5280/08

1 Page





AS8C401825-QC75N pdf, ピン配列
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Functional Block Diagram
Commercial Temperature Range
LBO
ADV
CLK
ADSC
ADSP
A0 - A16/17
GW
BWE
BW1
BW2
BW3
BW4
CLK EN
ADDRESS
REGISTER
Byte 1
Write Register
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
CEN
Binary
Counter
CLR
2
Burst
Sequence
Burst
Logic
Q0
Q1
A0*
A1*
17/18
2
A0,A1
A2 - A17
INTERNAL
ADDRESS
17/18
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
36/18
36/18
Byte 1
Write Driver
9
Byte 2
Write Driver
9
Byte 3
Write Driver
9
Byte 4
Write Driver
9
CE
CS0
CS1
ZZ
Powerdown
DQ
Enable
Register
CLK EN
DATA INPUT
REGISTER
OE
I/O0 - I/O31
I/OP1 - I/OP4
36/18
TMS
TDI
TCK
TRST
(Optional)
JTAG
(SA Version)
TDO
OE OUTPUT
BUFFER
,
5280 drw 01
6.342AA


3Pages


AS8C401825-QC75N 電子部品, 半導体
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Pin Configuration – 256K x 18
Commercial and Industrial Temperature Ra nges
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VSS(1)
VDD
NC
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(2)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
,
5280 drw 02b
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.462

6 Page



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部品番号部品説明メーカ
AS8C401825-QC75N

3.3V Synchronous SRAMs

Alliance Semiconductor
Alliance Semiconductor


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