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PDF TM104SDH02 Data sheet ( Hoja de datos )
| Número de pieza | TM104SDH02 | |
| Descripción | Display Module | |
| Fabricantes | TIANMA | |
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SHANGHAI TIANMA MICRO-ELECTRONICS
Coversheet
TM104SDH02 V1.1
MODEL NO. :
ISSUED DATE:
VERSION
:
TM104SDH02
2010-06-28
Ver 1.1
■Preliminary Specification
□Final Product Specification
Customer :
Approved by
Notes
SHANGHAI TIANMA Confirmed :
Prepared by
Checked by
Approved by
This technical specification is subjected to change without notice
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 1 of 21
1 page  
SHANGHAI TIANMA MICRO-ELECTRONICS
TM104SDH02 V1.1
2 Input/Output Terminals
2.1 TFT LCD Panel
CN1 Connector type:107A20-0021RA-G3-R
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
VDD
VDD
GND
DPS
RxIN0-
RxIN0+
GND
RxIN1-
RxIN1+
GND
RxIN2-
RxIN2+
GND
RxCLKIN-
RxCLKIN+
GND
I/O Description
P Power Supply
Comment
P Power Supply
P Ground
I Reverse Scan Function [H: Enable; L/NC: Disable]
Note3
I
I
LVDS receiver signal channel 0. LVDS Differential
Data Input (R0, R1, R2, R3, R4, R5, G0)
Note2
P Ground
I
I
LVDS receiver signal channel 1. LVDS Differential
Data Input (G1, G2, G3, G4, G5, B0, B1)
Note2
P Ground
I LVDS receiver signal channel 2
I LVDS Differential Data Input (B2, B3, B4, B5, DE)
Note2
P Ground
I
LVDS receiver signal clock
I
Note2
P Ground
17 RxIN3-
18 RxIN3+
I LVDS receiver signal channel 3, NC for 6 bit LVDS
Input. LVDS Differential Data Input (R6, R7, G6, G7, Note2
I B6, B7, RSV) for 8 bit LVDS input.
19 AG Mode
I
Aging Mode setting
[H: Aging Mode; L/NC: Normal]
20 SEL68
P
6/8bits LVDS data input selection
[H: 8bits L/NC: 6bit]
P: Power/GND; I: input pin;
Table 2.1 input terminal pin assignment
Note1: CN1 Match Connector type : DF19G-20S-1C or compatible
Note2: LVDS 6-bit data mapping when SEL68=L/NC as follows:
Note2
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 5 of 21
5 Page 
SHANGHAI TIANMA MICRO-ELECTRONICS
5.2 Power On/Off Sequence
Item
Symbol Min
Typ
VDD 3.0V to signal starting Tp1 5
-
Signal starting to backlight on Tp2 150
-
Signal off to VDD 3.0V
Tp3 5
-
Backlight off to signal off
Tp4 150
-
Max
50
-
50
-
TM104SDH02 V1.1
Unit
ms
ms
ms
ms
Remark
3.3V
VDD
Tp1
Tp3
3.3V
Signal
Backlight
Tp2
Tp4
Figure 5.2 Interface power on/off sequence
5.3 APPLICATION NOTES
5.3.1 Recommended Input Timing of LVDS transmitter
Parameter
Symbol
Min.
Typ.
Dclk frequency
1/Tclk
32
40
Horizontal
section
Horizontal total
Horizontal blanking
Valid Data Width
Th
Thb
Thd
866 1056
66 256
800 800
Frame rate
- - 60
Vertical Vertical total
section Vertical blanking
Tv 604 628
Tvb 4 28
Valid Data Width
Tvd 600 600
Note: DE signal is necessary.
Input Timing Control Conditions
Max.
50
1064
264
800
70
800
200
600
Unit
MHz
Tclk
Tclk
Tclk
Hz
Th
Th
Th
Remarks
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet TM104SDH02.PDF ] | |
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