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A3946 の電気的特性と機能

A3946のメーカーはAllegro MicroSystemsです、この部品の機能は「Half-Bridge Power MOSFET Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 A3946
部品説明 Half-Bridge Power MOSFET Controller
メーカ Allegro MicroSystems
ロゴ Allegro MicroSystems ロゴ 




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A3946 Datasheet, A3946 PDF,ピン配置, 機能
A3946
Half-Bridge Power MOSFET Controller
Features and Benefits
On-chip charge pump for 7 V minimum input
supply voltage
High-current gate drive for driving a wide range of
N-channel MOSFETs
Bootstrapped gate drive with top-off charge pump
for 100% duty cycle
Overtemperature protection
Undervoltage protection
–40ºC to 135ºC ambient operation
Packages:
16-pin SOICW (suffix LB)
16-pin TSSOP with exposed
thermal pad (suffix LP)
Description
TheA3946 is designed specifically for applications that require
high power unidirectional DC motors, three-phase brushless DC
motors, or other inductive loads. The A3946 provides two
high-current gate drive outputs that are capable of driving a
wide range of power N-channel MOSFETs. The high-side gate
driver switches an N-channel MOSFET that controls current to
the load, while the low-side gate driver switches an N-channel
MOSFET as a synchronous rectifier.
Abootstrap capacitor provides the above-battery supply voltage
required for N-channel MOSFETs. An internal top-off charge
pump for the high side allows DC (100% duty cycle) operation
of the half-bridge.
The A3946 is available in a choice of two power packages:
a 16-lead SOIC with two internally-fused pins for enhanced
power dissipation (part number suffix LB), and a 16-lead
TSSOP with exposed thermal pad (suffix LP). Both packages
have a lead (Pb) free version, with 100% matte tin plated
leadframes (suffix -T).
Approximate Scale 1:1
Typical Application
VBAT
ECU
VBB
~FAULT
BOOT
GH
IN1
IN2
RESET
A3946
S
GL
CP1
DT
VREF
CP2
VREG
LGND
PGND
M
29319.150h

1 Page





A3946 pdf, ピン配列
A3946
Half-Bridge Power MOSFET Controller
Functional Block Diagram
C2
0.47 uF, X7R
V rated to VBAT
P
VBB
C1
0.47 uF, X7R
V rated to VBAT
CP2
CP1
+VBAT
VREF
0.1 uF
X7R
10 10 V
k7 L
~FAULT
VREF
DT
+5 Vref
Charge
Pump
LP
ILIM
Top-Off
Charge Pump
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
L
Turn-On
Delay
High Side
Driver
VREG
BOOT
CREG
P
CBOOT
GH RGATE
P
RDEAD
L
IN1
IN2
L
RESET
L
Control
Logic
S
VREG
Low Side
Driver
P
L
GL RGATE
PGND
LGND
L
P
Control Logic Table
IN1 IN2
XX
DT Pin
X
0 0 RDEAD - LGND
0 1 RDEAD - LGND
1 0 RDEAD - LGND
1 1 RDEAD - LGND
00
VREF
01
10
VREF
VREF
11
VREF
RESET
0
1
1
1
1
1
1
1
1
GH
Z
L
L
L
H
L
L
H
H
GL Function
Z Sleep mode
H Low-side FET ON following dead time
L All OFF
L All OFF
L High-side FET ON following dead time
L All OFF
H Low-side FET ON
L High-side FET ON
H CAUTION: High-side and low-side FETs ON
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3


3Pages


A3946 電子部品, 半導体
A3946
Half-Bridge Power MOSFET Controller
Functional Description
VREG. A 13 V output from the on-chip charge pump, used
to power the low-side gate drive circuit directly, provides the
current to charge the bootstrap capacitors for the high-side gate
drive.
The VREG capacitor, CREG, must supply the instantaneous cur-
rent to the gate of the low-side MOSFET. A 10 μF, 25 V capaci-
tor should be adequate. This capacitor can be either electrolytic
or ceramic (X7R).
Diagnostics and Protection. The fault output pin,
~FAULT, goes low (i.e., FAULT = 1) when the RESET line is
high and any of the following conditions are present:
• Undervoltage on VREG (UVREG). Note that the outputs
become active as soon as VREG comes out of undervoltage,
even though the ~FAULT pin is latched until reset.
• Undervoltage on VREF (UVREF). Note that this condition
does NOT latch a fault.
• A junction temperature > 170°C (OVERTEMP). This condi-
tion sets a latched fault.
• An undervoltage on the stored charge of the BOOT capacitor
(UVBOOT). This condition does NOT set a latched fault.
An overtemperature event signals a latched fault, but does not
disable any output drivers, regulators, or logic inputs. The user
must turn off the A3946 (e.g., force the RESET line low) to
prevent damage.
possible UVBOOT), FAULT = 0; also the fault latch is cleared
immediately, and remains cleared. If the power is restored
(no UVREG or UVREF), and if no OVERTEMP fault exists,
then the latched fault remains cleared when the RESET line
returns to high. However, FAULT = 1 may still occur because a
UVBOOT fault condition may still exist.
Charge Pump. The A3946 is designed to accommodate a
wide range of power supply voltages. The charge pump output,
VREG, is regulated to 13 V nominal.
In all modes, this regulator is current-limited. When VBB < 8 V,
the charge pump operates as a voltage doubler. When 8 V <
VBB< 15 V, the charge pump operates as a voltage doubler/
PWM, current-controlled, voltage regulator. When VBB>15 V,
the charge pump operates as a PWM, current-controlled, volt-
age regulator. Efciency shifts, from 80% at VBB= 7 V, to 20%
at VBB = 50 V.
CAUTION. Although simple paralleling of VREG supplies
from several A3946s may appear to work correctly, such a
conguration is NOT recommended. There is no assurance that
one of the regulators will not dominate, taking on all of the load
and back-biasing the other regulators. (For example, this could
occur if a particular regulator has an internal reference voltage
that is higher that those of the other regulators, which would
force it to regulate at the highest voltage.)
The power FETs are protected from inadequate gate drive
voltage by undervoltage detectors. Either of the regulator
undervoltage faults (UVREG or UVREF) disable both output
drivers until both voltages have been restored. The high-side
driver is also disabled during a UVBOOT fault condition.
Under many operating conditions, both the high-side (GH)
and low-side (GL) drivers may be off, allowing the BOOT
capacitor to discharge (or never become charged) and create a
UVBOOT fault condition, which in turn inhibits the high-side
driver and creates a FAULT = 1. This fault is NOT latched. To
remove this fault, momentarily turn on GL to charge the BOOT
capacitor.
Latched faults may be cleared by a low pulse, 1 to 10 μs
wide, on the RESET line. Throughout that pulse (despite a
Sleep Mode/Power Up. In Sleep Mode, all circuits are
disabled in order to draw minimum current from VBB. When
powering up and leaving Sleep Mode (the RESET line is high),
the gate drive outputs stay disabled and a fault remains asserted
until VREF and VREG pass their undervoltage thresholds.
When powering up, before starting the rst bootstrap charge
cycle, wait until t = CREG 4 (where CREG is in μF, and t is in ns)
to allow the charge pump to stabilize.
When powered-up (not in Sleep Mode), if the RESET line is
low for > 10 μs, the A3946 may start to enter Sleep Mode (VREF
< 4 V). In that case, ~FAULT = 1 as long as the RESET line
remains low.
If the RESET line is open, the A3946 should go into Sleep
Mode. However, to ensure that this occurs, the RESET line
must be grounded.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6

6 Page



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