DataSheet.jp

HD1-15530-8 の電気的特性と機能

HD1-15530-8のメーカーはIntersil Corporationです、この部品の機能は「CMOS Manchester Encoder-Decoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 HD1-15530-8
部品説明 CMOS Manchester Encoder-Decoder
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




このページの下部にプレビューとHD1-15530-8ダウンロード(pdfファイル)リンクがあります。

Total 12 pages

No Preview Available !

HD1-15530-8 Datasheet, HD1-15530-8 PDF,ピン配置, 機能
HD-15530
March 1997
CMOS Manchester Encoder-Decoder
Features
Description
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
SMD#
PDIP
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
1.25 MEGABIT/s PKG. NO.
HD1-15530-9
F24.6
HD1-15530-8
7802901JA
HD4-15530-9
J28.A
HD4-15530-8
78029013A
HD3-15530-9
E24.6
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for the
Master Reset functions.
This circuit meets many of the requirements of MIL-STD-
1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decod-
ing the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmen-
tal control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
Pinouts
HD-15530 (CERDIP, PDIP)
TOP VIEW
VALID WORD 1
ENCODER
SHIFT CLK
2
TAKE DATA 3
SERIAL DATA OUT 4
DECODER CLK 5
BIPOLAR ZERO IN 6
BIPOLAR ONE IN 7
UNIPOLAR DATA IN 8
DECODER SHIFT CLK 9
COMMAND/
DATA SYNC
10
DECODER RESET 11
GND 12
24 VCC
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15
BIPOLAR
ZERO OUT
14 ÷ 6 OUT
13 MASTER RESET
HD-15530 (CLCC)
TOP VIEW
4 3 2 1 28 27 26
DECODER
CLK
5
25
SEND
DATA
NC 6
24 NC
NC 7
23 NC
BIPOLAR
ZERO IN
8
22
SYNC
SELECT
BIPOLAR
ONE IN
9
21
ENCODER
ENABLE
UNIPOLAR
DATA IN
10
20
SERIAL
DATA IN
DECODER
SHIFT CLK
11
19
BIPOLAR
ONE OUT
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-142
File Number 2960.1

1 Page





HD1-15530-8 pdf, ピン配列
HD-15530
Pin Description (Continued)
PIN
NUMBER
18
TYPE
NAME
I SERIAL DATA IN
19 I ENCODER ENABLE
20 I SYNC SELECT
21 O SEND DATA
22 I SEND CLOCK IN
23 I ENCODER CLOCK
24 I VCC
I = Input O = Output
SECTION
DESCRIPTION
Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
Encoder A high on this pin initiates the encode cycle. (Subject to the preceeding
cycle being complete.)
Encoder Actuates a Command sync for an input high and Data sync for an input low.
Encoder An active high output which enables the external source of serial data.
Encoder Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6
output.
Encoder Input to the 6:1 divider, a frequency equal to the data rate X12 is usually
input here.
Both
VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC
(pin 24) to GROUND (pin 12) is recommended.
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK 1 .
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word 2 . When the Encoder is ready to accept data,
the SEND DATA output will go high and remain high for six-
teen ENCODER SHIFT CLOCK periods 3 . During these
sixteen periods the data should be clocked into the SERIAL
DATA input with every high-to-low transition of the
ENCODER SHIFT CLOCK so it can be sampled on the low-
to-high transition 3 - 4 . After the sync and Manchester II
coded data are transmitted through the BIPOLAR ONE and
BIPOLAR ZERO outputs, the Encoder adds on an additional
bit which is the parity for that word 5 . If ENCODER
ENABLE is held high continuously, consecutive words will be
encoded without an interframe gap. ENCODER ENABLE
must go low by time 5 as shown to prevent a consecutive
word from being encoded. At any time a low on OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
TIMING
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
SYNC SELECT
SEND DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
0 1 23 4 5 6 7
15 16 17 18 19
VALID
DON’T CARE
DON’T CARE
15 14 13 12 11 10 3 2 1 0
1ST HALF 2ND HALF 15 14 13 12 11
3 210
SYNC SYNC 15 14 13 12 11
3 210
P
P
12
3
FIGURE 1.
45
5-144


3Pages


HD1-15530-8 電子部品, 半導体
HD-15530
MIL-STD-1553
The 1553 standard defines a time division multiplexed data
bus for application within aircraft. The bus is defined to be
bipolar, and encoded in a Manchester II format, so no DC
component appears on the bus. This allows transformer
coupling and excellent isolation among systems and their
environment.
The HD-15530 supports the full bipolar configuration,
assuming a bus driver configuration similar to that in Figure
1. Bipolar inputs from the bus, like Figure 2, are also accom-
modated.
The signaling format in MlL-STD-1553 is specified on the
assumption that the network of 32 or fewer terminals are
controlled by a central control unit by means of Command
Words. Terminals respond with Status Words. Each word is
preceded by a synchronizing pulse, and followed by parity
bit, occupying a total of 20µs. The word formats are shown in
Figure 4. The special abbreviations are as follows:
P Parity, which is defined to be odd, taken across all 17
bits.
R/T Receive on logical zero, transmit on ONE.
ME Message Error if logical 1.
TF Terminal Flat, if set, calls for controller to request
self-test data.
The paragraphs above are intended only to suggest the
content of MlL-STD-1553, and do not completely describe its
bus requirements, timing or protocols.
BUS
“1”
“0”
FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIVER
+
-
“1” REF
“0” REF
-
+
“1”
“0”
BUS
FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER
COMMAND
SYNC
DATA
SYNC
BIT
PERIOD
BIT
PERIOD
BIT
PERIOD
LOGICAL ONE DATA
LOGICAL ZERO DATA
FIGURE 8. MIL-STD-1553 CHARACTER FORMATS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
COMMAND WORD (FROM CONTROLLER TO TERMINAL)
SYNC
5
TERMINAL
ADDRESS
15
SUB ADDRESS
/MODE
R/T
5
DATA WORD
COUNT
1
P
DATA WORD (SENT EITHER DIRECTION)
16
SYNC
CONTROL WORD
1
P
STATUS WORD (FROM TERMINAL TO CONTROLLER)
SYNC
5
TERMINAL
ADDRESS
1 9 11
CODE FOR FAILURE MODES TF P
ME
FIGURE 9. MIL-STD-1553 WORD FORMATS
NOTE: This page is a summary of MIL-STD-1553 and is not intended to describe the operation of the HD-15530.
5-147

6 Page



ページ 合計 : 12 ページ
 
PDF
ダウンロード
[ HD1-15530-8 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
HD1-15530-8

CMOS Manchester Encoder-Decoder

Intersil Corporation
Intersil Corporation
HD1-15530-9

CMOS Manchester Encoder-Decoder

Intersil Corporation
Intersil Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap