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PDF HCTS374MS Data sheet ( Hoja de datos )
| Número de pieza | HCTS374MS | |
| Descripción | Radiation Hardened Octal D-Type Flip-Flop/ Three-State/ Positive Edge Triggered | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HCTS4002MS
August 1995
Radiation Hardened
Dual 4-Input NOR Gate
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL
PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14
TOP VIEW
Y1 1
A1 2
B1 3
C1 4
D1 5
NC 6
GND 7
14 VCC
13 Y2
12 D2
11 C2
10 B2
9 A2
8 NC
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS4002MS is a Radiation Hardened Dual 4-Input
NOR Gate. A high on any input forces the output to a low state.
The HCTS4002MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS4002MS is supplied in a 14 lead Ceramic flatpack (K
suffix) or a SBDIP Package (D suffix).
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14
TOP VIEW
Y1
A1
B1
C1
D1
NC
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
Y2
D2
C2
B2
A2
NC
Functional Diagram
An
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCTS4002DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
HCTS4002KMSR -55oC to +125oC Intersil Class
S Equivalent
14 Lead
Ceramic
Flatpack
HCTS4002D/
Sample
+25oC
Sample
14 Lead SBDIP
HCTS4002K/
Sample
+25oC
Sample
14 Lead
Ceramic
Flatpack
HCTS4002HMSR
+25oC
Die
Die
Bn
Yn
Cn
Dn
TRUTH TABLE
INPUTS
OUTPUTS
An Bn Cn Dn
Yn
LLLL
H
HXXX
L
XHXX
L
XXHX
L
XXXH
L
NOTE: L = Logic Level Low, H = Logic level High,
X = Don’t Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
718
Spec Number 518632
File Number 3075.1
1 page  
Specifications HCTS4002MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
1, 6, 8, 13
2 - 5, 7, 9 - 12
-
14 - -
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
1, 6, 8, 13
7
-
2 - 5, 9 - 12, 14
-
-
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
6, 8
7
1, 13
14 2 - 5, 9 - 12 -
NOTES:
1. Each pin except VCC and GND will have a resistor of 10kΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
1, 6, 8, 13
7
2 - 5, 9 - 12, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518632
722
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HCTS374MS.PDF ] | |
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