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PDF IP4284CZ10-TT Data sheet ( Hoja de datos )
| Número de pieza | IP4284CZ10-TT | |
| Descripción | ESD protection | |
| Fabricantes | NXP Semiconductors | |
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IP4284CZ10-TB; IP4284CZ10-TT
ESD protection for ultra high-speed interfaces
Rev. 02 — 1 April 2010
Product data sheet
1. Product profile
1.1 General description
The devices are designed to protect high-speed interfaces such as High-Definition
Multimedia Interface (HDMI), DisplayPort, SuperSpeed USB, external Serial Advanced
Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS) interfaces
against ElectroStatic Discharge (ESD).
The devices include high-level ESD protection diodes for ultra high-speed signal lines and
are available in two package variants: XSON10U and TSSOP10.
All signal lines are protected by a special diode configuration offering ultra low line
capacitance of only 0.5 pF. These diodes provide protection to downstream components
from ESD voltages up to ±8 kV contact according to IEC 61000-4-2, level 4.
1.2 Features and benefits
Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen
and antimony (Dark Green compliant)
System ESD protection for USB 2.0 and USB SuperSpeed 3.0, HDMI 1.3 and
HDMI 1.4, DisplayPort, eSATA and LVDS
All signal lines with integrated rail-to-rail clamping diodes for downstream
ESD protection of ±8 kV according to IEC 61000-4-2, level 4
Matched 0.5 mm trace spacing
Signal lines with ≤ 0.05 pF matching capacitance between signal pairs
Line capacitance of only 0.5 pF for each channel
4-channel, XSON10U or TSSOP10 Pb-free package
Design-friendly ’pass-thru’ signal routing
1.3 Applications
The devices are designed for high-speed receiver and transmitter port protection:
TVs, monitors
DVD recorders and players
Notebooks, mother boards, graphic cards and ports
Set-top boxes and game consoles
1 page  
NXP Semiconductors
IP4284CZ10-TB/TT
ESD protection for ultra high-speed interfaces
5 Gbit/s; USB 3.0 CP0 pattern
Fig 3. Eye diagram using reference PCB
0.4
Cd
(pF)
0.2
018aaa004
5 Gbit/s; USB 3.0 CP0 pattern
Fig 4. Eye diagram using IP4284CZ10-TB
018aaa006
018aaa005
(1)
0.0
(2)
−0.2
−0.4
−0.5
1.5
3.5 5.5
Vbias (V)
(1) Pin 2
(2) Pin 1
Deviation from typical capacitance normalized at Vbias = 2.5 V
Fig 5. Line capacitance as a function of bias voltage; typical values
IP4284CZ10-TB_TT_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 1 April 2010
© NXP B.V. 2010. All rights reserved.
5 of 15
5 Page 
NXP Semiconductors
IP4284CZ10-TB/TT
ESD protection for ultra high-speed interfaces
8. Abbreviations
Table 5. Abbreviations
Acronym
Description
DVD
Digital Versatile Disc
eSATA
external Serial Advanced Technology Attachment
ESD
ElectroStatic Discharge
HBM
Human Body Model
HDMI
High-Definition Multimedia Interface
LVDS
Low Voltage Differential Signaling
NEXT
Near End Crosstalk
RoHS
Restriction of Hazardous Substances
TLP Transmission Line Pulse
TMDS
Transition Minimized Differential Signaling
UTLP
Ultra Thin Leadless Package
IP4284CZ10-TB_TT_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 1 April 2010
© NXP B.V. 2010. All rights reserved.
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