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PDF TK4A50D Data sheet ( Hoja de datos )

Número de pieza TK4A50D
Descripción Field Effect Transistor
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



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No Preview Available ! TK4A50D Hoja de datos, Descripción, Manual

TK4A50D
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (π-MOS)
TK4A50D
Switching Regulator Applications
Low drain-source ON-resistance: RDS (ON) = 1.7Ω(typ.)
High forward transfer admittance: |Yfs| = 1.5 S (typ.)
Low leakage current: IDSS = 10 μA (max) (VDS = 500 V)
Enhancement mode: Vth = 2.4 to 4.4 V (VDS = 10 V, ID = 1 mA)
Unit: mm
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Drain-source voltage
Gate-source voltage
Drain current
DC (Note 1)
Pulse (t = 1 ms)
(Note 1)
Drain power dissipation (Tc = 25°C)
Single pulse avalanche energy
(Note 2)
Avalanche current
Repetitive avalanche energy (Note 3)
Channel temperature
Storage temperature range
VDSS
VGSS
ID
IDP
PD
EAS
IAR
EAR
Tch
Tstg
500
±30
4
16
30
156
4
3.0
150
55 to 150
V
V
A
W
mJ
A
mJ
°C
°C
1: Gate
2: Drain
3: Source
JEDEC
JEITA
SC-67
TOSHIBA
2-10U1B
Weight: 1.7 g (typ.)
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability
Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e.
reliability test report and estimated failure rate, etc).
Thermal Characteristics
Characteristics
Symbol
Max Unit
Thermal resistance, channel to case
Rth (ch-c)
4.17 °C/W
Thermal resistance, channel to ambient
Rth (ch-a)
62.5 °C/W
Note 1:Ensure that the channel temperature does not exceed 150.
Note 2: VDD = 90 V, Tch = 25°C (initial), L = 17 mH, RG = 25 Ω, IAR = 4 A
Note 3: Repetitive rating: pulse width limited by maximum channel temperature
This transistor is an electrostatic-sensitive device. Handle with care.
1
2
3
Start of commercial production
2008-11
1 2013-11-01

1 page




TK4A50D pdf
TK4A50D
rth – tw
10
1
Duty=0.5
0.2
0.1
0.1 0.05
0.02
0.01
0.01
0.001
10μ
100μ
SINGLE PULSE
PDM
t
T
Duty = t/T
Rth (ch-c) = 4.17 °C/W
1m
10m
100m
PULSE WIDTH tw (s)
1
10
SAFE OPERATING AREA
100
ID max (pulsed) *
10
ID max (continuous)
1 DC operation
Tc = 25°C
100 μs *
1 ms *
0.1
0.01
*: SINGLE NONREPETITIVE
PULSE Tc = 25°C
CURVES MUST BE DERATED
LINEARLY WITH INCREASE
IN TEMPERATURE.
0.001
0.1 1 10
VDSS max
100
1000
DRAIN-SOURCE VOLTAGE VDS (V)
EAS – Tch
180
160
140
120
100
80
60
40
20
0
25 50 75 100 125 150
CHANNEL TEMPEATURE (INITIAL)
Tch(°C)
15 V
15 V
BVDSS
IAR
VDD
VDS
TEST CIRCUIT
WAVEFORM
RG = 25 Ω
VDD = 90 V, L = 17 mH
ΕAS
=
1
2
L
I2
⎜⎜⎝⎛
BVDSS
BVDSS VDD
⎟⎟⎠⎞
5 2013-11-01

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