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PDF HCTS30KMSR Data sheet ( Hoja de datos )
| Número de pieza | HCTS30KMSR | |
| Descripción | Radiation Hardened 8-Input NAND Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HCTS32MS
September 1995
Radiation Hardened
Quad 2-Input OR Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA @ VOL, VOH
Description
The Intersil HCTS32MS is a Radiation Hardened Quad 2-Input OR
Gate. A Low on all inputs forces the output to a Low state.
The HCTS32MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
A1
B1
Y1
A2
B2
Y2
GND
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
VCC
B4
A4
Y4
B3
A3
Y3
The HCTS32MS is supplied in a 14 lead Ceramic flatpack (K
suffix) or a SBDIP Package (D suffix).
Ordering Information
Functional Diagram
An
(1, 4, 9, 12)
PART
NUMBER
HCTS32DMSR
HCTS32KMSR
HCTS32D/
Sample
HCTS32K/
Sample
HCTS32HMSR
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
-55oC to +125oC Intersil Class
S Equivalent
14 Lead SBDIP
-55oC to +125oC Intersil Class
S Equivalent
14 Lead
Ceramic
Flatpack
+25oC
Sample
14 Lead SBDIP
+25oC
Sample
+25oC
Die
14 Lead
Ceramic
Flatpack
Die
Bn
(2, 5, 10, 13)
TRUTH TABLE
INPUTS
An Bn
LL
LH
HL
HH
Yn
(3, 6, 8, 11)
OUTPUTS
Yn
L
H
H
H
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
450
Spec Number 518638
File Number 2248.2
1 page  
Specifications HCTS32MS
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE
GROUPS
METHOD
TEST
PRE RAD
POST RAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
READ AND RECORD
PRE RAD
POST RAD
1, 9 Table 4 (Note 1)
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
3, 6, 8, 11
1, 2, 4, 5, 7, 9, 10,
12, 13
-
14 - -
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
3, 6, 8, 11
7
-
1, 2, 4, 5, 9, 10, 12,
-
13, 14
-
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
7
3, 6, 8, 11
14 1, 2, 4, 5, 9, 10, 12,
-
13
NOTES:
1. Each pin except VCC and GND will have a resistor of 10kΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1kΩ ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518638
454
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| PDF Descargar | [ Datasheet HCTS30KMSR.PDF ] | |
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