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PSMN3R0-30YLD の電気的特性と機能

PSMN3R0-30YLDのメーカーはNXP Semiconductorsです、この部品の機能は「N-channel MOSFET」です。


製品の詳細 ( Datasheet PDF )

部品番号 PSMN3R0-30YLD
部品説明 N-channel MOSFET
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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PSMN3R0-30YLD Datasheet, PSMN3R0-30YLD PDF,ピン配置, 機能
PSMN3R0-30YLD
N-channel 30 V, 3.0 mΩ logic level MOSFET in LFPAK56
using NextPowerS3 Technology
18 February 2014
Product data sheet
1. General description
Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package.
NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers
high efficiency, low spiking performance usually associated with MOSFETs with an
integrated Schottky or Schottky-like diode but without problematic high leakage current.
NextPowerS3 is particularly suited to high efficiency applications at high switching
frequencies.
2. Features and benefits
Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching
frequencies
Superfast switching with soft-recovery; s-factor > 1
Low spiking and ringing for low EMI designs
Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at
25 °C
Optimised for 4.5 V gate drive
Low parasitic inductance and resistance
High reliability clip bonded and solder die attach Power SO8 package; no glue, no
wire bonds, qualified to 175 °C
Wave solderable; exposed leads for optimal visual solder inspection
3. Applications
On-board DC-to-DC solutions for server and telecommunications
Secondary-side synchronous rectification in telecommunication applications
Voltage regulator modules (VRM)
Point-of-Load (POL) modules
Power delivery for V-core, ASIC, DDR, GPU, VGA and system components
Brushed and brushless motor control
4. Quick reference data
Table 1.
Symbol
VDS
ID
Ptot
Quick reference data
Parameter
Conditions
drain-source voltage 25 °C ≤ Tj ≤ 175 °C
drain current
Tmb = 25 °C; VGS = 10 V; Fig. 2
total power dissipation Tmb = 25 °C; Fig. 1
Min Typ Max Unit
- - 30 V
[1] - - 100 A
- - 91 W
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PSMN3R0-30YLD pdf, ピン配列
NXP Semiconductors
7. Marking
Table 4. Marking codes
Type number
PSMN3R0-30YLD
PSMN3R0-30YLD
N-channel 30 V, 3.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Marking code
3D030L
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C
VDGR
drain-gate voltage
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
VGS gate-source voltage
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
ID drain current
VGS = 10 V; Tmb = 25 °C; Fig. 2
VGS = 10 V; Tmb = 100 °C; Fig. 2
IDM peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
Tstg storage temperature
Tj junction temperature
Tsld(M)
peak soldering temperature
VESD
electrostatic discharge voltage HBM
Source-drain diode
IS source current
Tmb = 25 °C
ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 25 A;
Vsup ≤ 30 V; RGS = 50 Ω; unclamped;
tp = 467 µs
[1]
[2]
[1] Continuous current is limited by package.
[2] Protected by 100% test
Min Max Unit
- 30 V
- 30 V
-20 20
V
- 91 W
- 100 A
- 90 A
- 512 A
-55 175 °C
-55 175 °C
- 260 °C
500 -
V
- 76 A
- 512 A
- 227.5 mJ
PSMN3R0-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
18 February 2014
© NXP N.V. 2014. All rights reserved
3 / 13


3Pages


PSMN3R0-30YLD 電子部品, 半導体
NXP Semiconductors
PSMN3R0-30YLD
N-channel 30 V, 3.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
ΔVGS(th)/ΔT
gate-source threshold
voltage variation with
temperature
25 °C < Tj < 150 °C
IDSS drain leakage current VDS = 24 V; VGS = 0 V; Tj = 25 °C
VDS = 24 V; VGS = 0 V; Tj = 125 °C
IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
RDSon
drain-source on-state VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
resistance
Fig. 10
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
Fig. 11; Fig. 10
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10
VGS = 10 V; ID = 25 A; Tj = 150 °C;
Fig. 11; Fig. 10
RG
gate resistance
f = 1 MHz
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 15 V; VGS = 10 V;
Fig. 12; Fig. 13
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 12; Fig. 13
ID = 0 A; VDS = 0 V; VGS = 10 V
QGS
QGS(th)
gate-source charge
pre-threshold gate-
source charge
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 12; Fig. 13
QGS(th-pl)
post-threshold gate-
source charge
QGD gate-drain charge
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13
Ciss
input capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 14
Crss reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V;
RG(ext) = 5 Ω
td(off)
turn-off delay time
tf fall time
Min Typ Max Unit
- -4.3 - mV/K
- - 1 µA
- 0.82 - µA
- - 100 nA
- - 100 nA
-
3.2 4
- - 6.6 mΩ
- 2.57 3.1 mΩ
- - 5.1 mΩ
- 0.57 1.14 Ω
- 31 46.4 nC
- 14.5 21.9 nC
- 28.5 - nC
- 4.9 - nC
- 2.9 - nC
- 2 - nC
- 4.5 6.7 nC
- 2.75 - V
- 1959 2939 pF
- 1029 1543 pF
- 140 210 pF
- 13.5 - ns
- 21 - ns
- 16.9 - ns
- 12.4 - ns
PSMN3R0-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
18 February 2014
© NXP N.V. 2014. All rights reserved
6 / 13

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共有リンク

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