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HCTS112D の電気的特性と機能

HCTS112DのメーカーはIntersil Corporationです、この部品の機能は「Radiation Hardened Dual JK Flip-Flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCTS112D
部品説明 Radiation Hardened Dual JK Flip-Flop
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HCTS112D Datasheet, HCTS112D PDF,ピン配置, 機能
HCTS112MS
September 1995
Radiation Hardened
Dual JK Flip-Flop
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Rate 2 x 10-9 Errors/Bit Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
CP1 1
K1 2
J1 3
S1 4
Q1 5
Q1 6
Q2 7
GND 8
16 VCC
15 R1
14 R2
13 CP2
12 K2
11 J2
10 S2
9 Q2
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCTS112MS is a Radiation Hardened dual JK
flip-flop with set and reset. The flip-flop changes states with
the negative transition of the clock (CP1N or CP2N).
The HCTS112MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
CP1
K1
J1
S1
Q1
Q1
Q2
GND
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
The HCTS112MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
VCC
R1
R2
CP2
K2
J2
S2
Q2
Ordering Information
PART NUMBER
HCTS112DMSR
HCTS112KMSR
HCTS112D/Sample
HCTS112K/Sample
HCTS112HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
490
Spec Number 518603
File Number 2467.2

1 Page





HCTS112D pdf, ピン配列
Specifications HCTS112MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . 100ns/V Max
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
SYMBOL
(NOTE 1)
CONDITIONS
ICC VCC = 5.5V,
VIN = VCC or GND
Output Current
(Sink)
IOL VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
IOH
VOL
VOH
IIN
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
VCC = 4.5V, VIH = 2.25V,
IOL = 50µA, VIL = 0.8V
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V
VCC = 4.5V, VIH = 2.25V,
IOH = -50µA, VIL = 0.8V
VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.8V
VCC = 5.5V, VIN = VCC or
GND
Noise Immunity
Functional Test
FN VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 2)
GROUP
A SUB-
GROUPS
1
2, 3
1
2, 3
1
2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2, 3
7, 8A, 8B
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC
+125oC, -55oC
+25oC, +125oC, -55oC
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
LIMITS
MIN MAX
- 20
- 400
4.8 -
4.0 -
-4.8 -
-4.0 -
- 0.1
- 0.1
VCC
-0.1
VCC
-0.1
-
-
-
±0.5
±5.0
-
UNITS
µA
µA
mA
mA
mA
mA
V
V
V
V
µA
µA
-
Spec Number 518603
492


3Pages


HCTS112D 電子部品, 半導体
Specifications HCTS112MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
Interim Test I (Postburn-In)
100%/5004
1, 7, 9
Interim Test II (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Interim Test III (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A (Note 1)
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Group D
Sample5005
1, 7, 9
NOTE:
1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised.
READ AND RECORD
ICC, IOL/H
ICC, IOL/H
ICC, IOL/H
ICC, IOL/H
Subgroups 1, 2, 3, 9, 10, 11
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE
GROUPS
METHOD
PRE RAD
Group E Subgroup 2
5005
1, 7, 9
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TEST
POST RAD
Table 4
READ AND RECORD
PRE RAD
POST RAD
1, 9 Table 4 (Note 1)
TABLE 8. STATIC BURN-IN AND DYNAMIC BURN-IN TEST CONNECTIONS
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
5, 6, 7, 9
1 - 4, 8, 10 - 15
-
16
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
5, 6, 7, 9
8
- 1 - 4, 10 - 16
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
8
5, 6, 7, 9
2, 3, 4, 10, 11, 12, 14, 15,
16
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
OSCILLATOR
50kHz
25kHz
--
--
1, 13
-
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
5, 6, 7, 9
8
1 - 4, 10 - 16
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518603
495

6 Page



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部品番号部品説明メーカ
HCTS112D

Radiation Hardened Dual JK Flip-Flop

Intersil Corporation
Intersil Corporation
HCTS112DMSR

Radiation Hardened Dual JK Flip-Flop

Intersil Corporation
Intersil Corporation
HCTS112HMSR

Radiation Hardened Dual JK Flip-Flop

Intersil Corporation
Intersil Corporation
HCTS112K

Radiation Hardened Dual JK Flip-Flop

Intersil Corporation
Intersil Corporation


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