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HCTS02MS の電気的特性と機能

HCTS02MSのメーカーはIntersil Corporationです、この部品の機能は「Radiation Hardened Quad 2-Input NOR Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCTS02MS
部品説明 Radiation Hardened Quad 2-Input NOR Gate
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HCTS02MS Datasheet, HCTS02MS PDF,ピン配置, 機能
HCTS02MS
August 1995
Radiation Hardened
Quad 2-Input NOR Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD(Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 Rads (Si)/s
• Dose Rate Upset >1010 RAD(Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCTS02MS is a Radiation Hardened Quad 2-Input
NOR Gate. A low on both inputs forces the output to a High state.
The HCTS02MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
Y1
A1
B1
Y2
A2
B2
GND
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
Y1 1
A1 2
B1 3
Y2 4
A2 5
B2 6
GND 7
14 VCC
13 Y4
12 B4
11 A4
10 Y3
9 B3
8 A3
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
VCC
Y4
B4
A4
Y3
B3
A3
The HCTS02MS is supplied in a 14 lead Ceramic Flatpack Pack-
age (K suffix) or a 14 lead SBDIP Package (D suffix).
TRUTH TABLE
INPUTS
OUTPUTS
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCTS02DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
HCTS02KMSR -55oC to +125oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCTS02D/
Sample
+25oC
Sample
14 Lead SBDIP
HCTS02K/
Sample
+25oC
Sample
14 Lead Ceramic
Flatpack
HCTS02HMSR
+25oC
Die
Die
An Bn Yn
L LH
LHL
HL L
HH L
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
An
(2, 5, 8, 11)
Bn
(3, 6, 9, 12)
Yn
(1, 4, 10, 13)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518841
File Number 2137.2

1 Page





HCTS02MS pdf, ピン配列
Specifications HCTS02MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Input to Output
SYMBOL
TPHL
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V
TPLH VCC = 4.5V
GROUP
A SUB-
GROUPS
9
10, 11
9
10, 11
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
LIMITS
MIN MAX UNITS
2 18 ns
2 20 ns
2 20 ns
2 22 ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Capacitance Power
Dissipation
SYMBOL
CPD
CONDITIONS
VCC = 5.0V, f = 1MHz
Input Capacitance
CIN VCC = 5.0V, f = 1MHz
Output Transition
Time
TTHL
TTLH
VCC = 4.5V
NOTES
TEMPERATURE
MIN
MAX UNITS
1
+25oC
- 45 pF
1
+125oC, -55oC
-
68 pF
1
+25oC
- 10 pF
1
+125oC
- 10 pF
1
+25oC
- 15 ns
1
+125oC
- 22 ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETERS
Quiescent Current
Output Current (Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage Current
Noise Immunity
Functional Test
Input to Output
SYMBOL
ICC
IOL
IOH
VOL
VOH
IIN
FN
TPHL
TPLH
(NOTES 1, 2)
CONDITIONS
VCC = 5.5V, VIN = VCC or GND
VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
VCC = 4.5V or 5.5V, VIH = VCC/2,
VIL = 0.8V at 200K RAD, IOL = 50µA
VCC = 4.5V or 5.5V, VIH = VCC/2,
VIL = 0.8V at 200K RAD, IOH = -50µA
VCC = 5.5V, VIN = VCC or GND
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V at 200K RAD, (Note 3)
VCC = 4.5V
VCC = 4.5V
TEMPERATURE
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
200K RAD LIMITS
MIN MAX
- 0.2
4.0 -
-4.0 -
- 0.1
VCC
-0.1
-5.0
-
-
+5.0
-
2 20
2 22
UNITS
mA
mA
mA
V
V
µA
-
ns
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
Spec Number 518841
3


3Pages


HCTS02MS 電子部品, 半導体
HCTS02MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PIND, Method 2020, Condition A
100% External Visual
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1 and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quan-
tity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number 518841
6

6 Page



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部品番号部品説明メーカ
HCTS02MS

Radiation Hardened Quad 2-Input NOR Gate

Intersil Corporation
Intersil Corporation


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