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HCS74T PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 HCS74T
部品説明 Radiation Hardened Dual-D Flip-Flop with Set and Reset
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 



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HCS74T Datasheet, HCS74T PDF,ピン配置, 機能
Data Sheet
HCS74T
July 1999 File Number 4615.1
Radiation Hardened Dual-D Flip-Flop with
Set and Reset
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The Intersil HCS74T is a Radiation Hardened Positive Edge
Triggered Flip-Flop with set and reset.
The HCS74T utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCS74T are
contained in SMD 5962-95782. A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Ordering Information
ORDERING
INFORMATION
PART
NUMBER
TEMP.
RANGE
(oC)
5962R9578201TCC
HCS74DTR
-55 to 125
5962R9578201TXC
HCS74KTR
-55 to 125
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
- Latch-Up Free Under Any Conditions, SOS Process
- SEP Effective LET No Upsets: >100 MEV-cm2/mg
- Single Event Upset (SEU) Immunity < 2 x 10-9
Errors/Bit-Day (Typ)
• 3 Micron Radiation Hardened SOS CMOS
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii 5µA at VOL, VOH
Pinouts
HCS74T (SBDIP), CDIP2-T14
TOP VIEW
R1 1
D1 2
CP1 3
S1N 4
Q1 5
Q1N 6
GND 7
14 VCC
13 R2N
12 D2
11 CP2
10 S2N
9 Q2
8 Q2N
R1
D1
CP1
S1
Q1
Q1
GND
HCS74T (FLATPACK), CDFP3-F14
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
VCC
R2
D2
CP2
S2
Q2
Q2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.

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