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HCS74DMSR の電気的特性と機能

HCS74DMSRのメーカーはIntersil Corporationです、この部品の機能は「Radiation Hardened Dual-D Flip-Flop with Set and Reset」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCS74DMSR
部品説明 Radiation Hardened Dual-D Flip-Flop with Set and Reset
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HCS74DMSR Datasheet, HCS74DMSR PDF,ピン配置, 機能
HCS74MS
September 1995
Radiation Hardened Dual-D
Flip-Flop with Set and Reset
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
R1N 1
D1 2
CP1 3
S1N 4
Q1 5
Q1N 6
GND 7
14 VCC
13 R2N
12 D2
11 CP2
10 S2N
9 Q2
8 Q2N
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCS74MS is a Radiation Hardened positive
edge triggered flip-flop with set and reset.
The HCS74MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS74MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
R1
D1
CP1
S1
Q1
Q1
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
R2
D2
CP2
S2
Q2
Q2
Ordering Information
PART NUMBER
HCS74DMSR
HCS74KMSR
HCS74D/Sample
HCS74K/Sample
HCS74HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
83
Spec Number 518772
File Number 2142.2

1 Page





HCS74DMSR pdf, ピン配列
Specifications HCS74MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . . 74oC/W 24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 116oC/W 30oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . 100ns/V Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
SYMBOL
(NOTE 1)
CONDITIONS
ICC VCC = 5.5V,
VIN = VCC or GND
Output Current
(Sink)
IOL VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
IOH
VOL
VOH
IIN
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
VCC = 4.5V, VIH = 3.15V,
IOL = 50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
VCC = 5.5V, VIN = VCC or
GND
Noise Immunity
Functional Test
FN VCC = 4.5V,
VIH = 0.70(VCC), (Note 2)
VIL = 0.30(VCC)
GROUP
A SUB-
GROUPS
1
2, 3
1
2, 3
1
2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2, 3
7, 8A, 8B
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC
+125oC, -55oC
+25oC, +125oC, -55oC
NOTES:
1. All voltages reference to device GND.
2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
LIMITS
MIN MAX
- 20
- 400
4.8 -
4.0 -
-4.8 -
-4.0 -
- 0.1
- 0.1
VCC
-0.1
VCC
-0.1
-
-
-
-
-
±0.5
±5.0
-
UNITS
µA
µA
mA
mA
mA
mA
V
V
V
V
µA
µA
-
Spec Number 518772
85


3Pages


HCS74DMSR 電子部品, 半導体
Specifications HCS74MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
Interim Test I (Postburn-In)
Interim Test II (Postburn-In)
PDA
Interim Test III (Postburn-In)
PDA
Final Test
Group A (Note 1)
Group B
Subgroup B-5
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
GROUP A SUBGROUPS
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Group D
Sample/5005
1, 7, 9
NOTES:
1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.
READ AND RECORD
ICC, IOL/H
ICC, IOL/H
ICC, IOL/H
ICC, IOL/H
Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE
GROUPS
METHOD
PRE RAD
Group E Subgroup 2
5005
1, 7, 9
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TEST
POST RAD
Table 4
READ AND RECORD
PRE RAD
POST RAD
1, 9 Table 4 (Note 1)
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
STATIC BURN-IN I TEST CONDITIONS (Note 1)
5, 6, 8, 9
1 - 4, 7, 10 - 13
-
14
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
5, 6, 8, 9
7
- 1, 2, 3, 4, 10, 11, 12,
13, 14
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
-
7
5, 6, 8, 9
1, 4, 10, 13, 14
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
OSCILLATOR
50kHz
25kHz
--
--
3, 11
2, 12
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
5, 6, 8, 9
7
1 - 4, 10 - 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518772
88

6 Page



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部品番号部品説明メーカ
HCS74DMSR

Radiation Hardened Dual-D Flip-Flop with Set and Reset

Intersil Corporation
Intersil Corporation


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