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HCS21D の電気的特性と機能

HCS21DのメーカーはIntersil Corporationです、この部品の機能は「Radiation Hardened Dual 4-Input AND Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCS21D
部品説明 Radiation Hardened Dual 4-Input AND Gate
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HCS21D Datasheet, HCS21D PDF,ピン配置, 機能
HCS21MS
September 1995
Radiation Hardened
Dual 4-Input AND Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
NC 3
C1 4
D1 5
Y1 6
GND 7
14 VCC
13 D2
12 C2
11 NC
10 B2
9 A2
8 Y2
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCS21MS is a Radiation Hardened Dual Input AND
Gate. A high on all inputs forces the output to a High state.
The HCS21MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCS21MS is supplied in a 14 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix).
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
NC
C1
D1
Y1
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
D2
C2
NC
B2
A2
Y2
Functional Diagram
An (1, 9)
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCS21DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
HCS21KMSR -55oC to +125oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCS21D/
Sample
+25oC
Sample
14 Lead SBDIP
HCS21K/
Sample
+25oC
Sample
14 Lead Ceramic
Flatpack
HCS21HMSR
+25oC
Die
Die
Bn (2, 10)
Cn (4, 12)
Dn (5, 13)
Yn (6, 8)
TRUTH TABLE
INPUTS
OUTPUTS
An Bn Cn Dn
Yn
LXXX
L
XLXX
L
XXLX
L
XXXL
L
H H HX H
H
NOTE: L = Logic Level Low, H = Logic level High, X = Don’t
Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
53
Spec Number 518762
File Number 3052.1

1 Page





HCS21D pdf, ピン配列
Specifications HCS21MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Input to Y
Input to YN
SYMBOL
TPHL
TPLH
TPHL
TPLH
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
GROUP
A SUB-
GROUPS
9
10, 11
9
10, 11
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
LIMITS
MIN MAX UNITS
2 18 ns
2 20 ns
2 20 ns
2 22 ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Capacitance Power
Dissipation
SYMBOL
CPD
CONDITIONS
VCC = 5.0V, f = 1MHz
Input Capacitance
CIN VCC = 5.0V, f = 1MHz
Output Transition
Time
TTHL
TTLH
VCC = 4.5V
NOTES
1
1
1
1
1
1
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
MIN MAX UNITS
- 39 pF
- 44 pF
- 10 pF
- 10 pF
- 15 ns
- 22 ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics..
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Output Current (Sink)
Output Current (Source)
Output Voltage Low
Output Voltage High
Input Leakage Current
Noise Immunity
Functional Test
Input to Y
SYMBOL
(NOTES 1, 2)
CONDITIONS
ICC VCC = 5.5V, VIN = VCC or GND
IOL VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
IOH VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
VOL
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOL = 50µA
VOH
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOH = -50µA
IIN VCC = 5.5V, VIN = VCC or GND
FN VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 3)
TPHL VCC = 4.5V
TPLH VCC = 4.5V
200K RAD LIMITS
TEMPERATURE
+25oC
+25oC
MIN
-
4.0
MAX
0.2
-
UNITS
mA
mA
+25oC
-4.0 - mA
+25oC
- 0.1 V
+25oC
+25oC
+25oC
VCC
-0.1
-
-
-
±5
-
V
µA
-
+25oC
+25oC
2 20 ns
2 22 ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
Spec Number 518762
55


3Pages


HCS21D 電子部品, 半導体
HCS21MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PIND, Method 2020, Condition A
100% External Visual
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number 518762
58

6 Page



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部品番号部品説明メーカ
HCS21D

Radiation Hardened Dual 4-Input AND Gate

Intersil Corporation
Intersil Corporation
HCS21DMSR

Radiation Hardened Dual 4-Input AND Gate

Intersil Corporation
Intersil Corporation
HCS21HMSR

Radiation Hardened Dual 4-Input AND Gate

Intersil Corporation
Intersil Corporation
HCS21K

Radiation Hardened Dual 4-Input AND Gate

Intersil Corporation
Intersil Corporation


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