HCS166DMSR Datasheet PDF - Intersil Corporation
| Part Number | HCS166DMSR | |
| Description | Radiation Hardened 8-Bit Parallel-Input/Serial Output Shift Register | |
| Manufacturers | Intersil Corporation | |
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HCS166MS
September 1995
Radiation Hardened 8-Bit
Parallel-Input/Serial Output Shift Register
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD s(Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Standard Outputs - 10 LSTTL Loads
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
DS 1
D0 2
D1 3
D2 4
D3 5
CE 6
CP 7
GND 8
16 VCC
15 PE
14 D7
13 Q7
12 D6
11 D5
10 D4
9 MR
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
Description
The Intersil HCS166MS is an 8-bit shift register that has fully
synchronous serial or parallel data entry selected by an
active LOW Parallel Enable (PE) input. When the PE is LOW
one setup time before the LOW-to-HIGH clock transition,
parallel data is entered into the register. When PE is HIGH,
data is entered into internal bit position Q0 from Serial Data
Input (DS), and the remaining bits are shifted one place to
the right (Q0 → Q1 → Q2m etc.) with each positive-going
clock transition. For expansion of the register in parallel to
serial converters, the Q7 output is connected to the DS input
of the succeeding stage.
DS
D0
D1
D2
D3
CE
CP
GND
1
2
3
4
5
6
7
8
Ordering Information
16
15
14
13
12
11
10
9
VCC
PE
D7
Q7
D6
D5
D4
MR
The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary and
con be reversed for layout convenience. The LOW-to-HIGH
transition of CE input should only take place while the CP is
HIGH for predictable operation.
A LOW on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.
The HCS166MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS166MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCS166DMSR -55oC to +125oC Intersil Class S 16 Lead
Equivalent
SBDIP
HCS166KMSR
-55oC to +125oC Intersil Class S 16 Lead
Equivalent
Ceramic
Flatpack
HCS166D/
Sample
+25oC
Sample
16 Lead
SBDIP
HCS166K/
Sample
+25oC
Sample
16 Lead
Ceramic
Flatpack
HCS166HMSR
+25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
250
Spec Number 518758
File Number 2482.2
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Specifications HCS166MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Output Current (Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage Current
Noise Immunity
Functional Test
CP or CE to Q7
MR to Q7
SYMBOL
(NOTES 1, 2)
CONDITIONS
ICC VCC = 5.5V, VIN = VCC or GND
IOL VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
IOH VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
VOL
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOL = 50µA
VOH
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOH = -50µA
IIN VCC = 5.5V, VIN = VCC or GND
FN VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 3)
TPHL VCC = 4.5V
TPLH VCC = 4.5V
TPHL VCC = 4.5V
TEMPERATURE
+25oC
+25oC
200K RAD
LIMITS
MIN MAX UNITS
- 0.75 mA
4.0 - mA
+25oC
-4.0 - mA
+25oC
- 0.1 V
+25oC
+25oC
+25oC
VCC
-0.1
-
-
-
±5
-
V
µA
-
+25oC
+25oC
+25oC
2 37 ns
2 37 ns
2 36 ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
PARAMETER
GROUP B
SUBGROUP
DELTA LIMIT
ICC 5 12µA
IOL/IOH
5 -15% of 0 Hour
Spec Number 518758
254
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| Information | Total 9 Pages | |
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