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HCS10MS の電気的特性と機能

HCS10MSのメーカーはIntersil Corporationです、この部品の機能は「Radiation Hardened Triple 3-Input NAND Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCS10MS
部品説明 Radiation Hardened Triple 3-Input NAND Gate
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HCS10MS Datasheet, HCS10MS PDF,ピン配置, 機能
HCS10MS
September 1995
Radiation Hardened
Triple 3-Input NAND Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (SI)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Gate Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-183S CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCS10MS is a Radiation Hardened Triple 3-Input
NAND Gate. A high on all inputs forces the output to a Low state.
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-183S CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
A2
B2
C2
Y2
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
C1
Y1
C3
B3
A3
Y3
The HCS10MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS10MS is supplied in a 14 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCS05DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
HCS05KMSR -55oC to +125oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCS05D/
Sample
+25oC
Sample
14 Lead SBDIP
HCS05K/
Sample
+25oC
Sample
14 Lead Ceramic
Flatpack
HCS05HMSR
+25oC
Die
Die
Functional Diagram
An
(1, 3, 9)
Bn
(2, 4, 10)
Cn
(5, 11, 13)
Yn
(12, 6, 8)
TRUTH TABLE
INPUTS
OUTPUTS
An Bn Cn
Yn
LLL
H
L LH
H
LHL
H
L HH
H
HL L
H
HLH
H
HH L
H
HHH
L
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number 518747
File Number 2435.2

1 Page





HCS10MS pdf, ピン配列
Specifications HCS10MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Input to Yn
SYMBOL
TPHL
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V
Input to Yn
TPLH VCC = 4.5V
GROUP
A SUB-
GROUPS
9
10, 11
9
10, 11
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
LIMITS
MIN MAX UNITS
2 18 ns
2 20 ns
2 20 ns
2 22 ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Capacitance Power
Dissipation
SYMBOL
CPD
CONDITIONS
VCC = 5.0V, f = 1MHz
Input Capacitance
CIN VCC = 5.0V, f = 1MHz
Output Transition
Time
TTHL
TTLH
VCC = 4.5V
NOTES
1
1
1
1
1
1
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
MIN MAX UNITS
- 39 pF
- 47 pF
- 10 pF
- 10 pF
- 15 ns
- 22 ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
Output Current (Sink)
Output Current (Source)
Output Voltage Low
Output Voltage High
Input Leakage Current
Noise Immunity
Functional Test
Input to Yn
SYMBOL
(NOTES 1, 2)
CONDITIONS
ICC VCC = 5.5V, VIN = VCC or GND
IOL VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
IOH VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
VOL
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOL = 50µA
VOH
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOH = -50µA
IIN VCC = 5.5V, VIN = VCC or GND
FN VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 3)
TPHL VCC = 4.5V
TPLH VCC = 4.5V
200K RAD LIMITS
TEMPERATURE
+25oC
+25oC
MIN
-
4.0
MAX
0.2
-
UNITS
mA
mA
+25oC
-4.0 - mA
+25oC
- 0.1 V
+25oC
+25oC
+25oC
VCC
-0.1
-
-
-
±5
-
V
µA
-
+25oC
+25oC
2 20 ns
2 22 ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
Spec Number 518747
3


3Pages


HCS10MS 電子部品, 半導体
HCS10MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PIND, Method 2020, Condition A
100% External Visual
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number 518747
6

6 Page



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部品番号部品説明メーカ
HCS10MS

Radiation Hardened Triple 3-Input NAND Gate

Intersil Corporation
Intersil Corporation


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