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HCS109D の電気的特性と機能

HCS109DのメーカーはIntersil Corporationです、この部品の機能は「Radiation Hardened Dual JK Flip Flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCS109D
部品説明 Radiation Hardened Dual JK Flip Flop
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HCS109D Datasheet, HCS109D PDF,ピン配置, 機能
HCS109MS
September 1995
Radiation Hardened
Dual JK Flip Flop
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
R1 1
J1 2
K1 3
CP1 4
S1 5
Q1 6
Q1 7
GND 8
16 VCC
15 R2
14 J2
13 K2
12 CP2
11 S2
10 Q2
9 Q2
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCS109MS is a Radiation Hardened Dual JK
Flip Flop with set and reset. The flip flop changes state with
the positive transition of the clock (CP1 or CP2).
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
R1
J1
K1
CP1
S1
Q1
Q1
GND
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VCC
R2
J2
K2
CP2
S2
Q2
Q2
The HCS109MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS109MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCS109DMSR
HCS109KMSR
HCS109D/Sample
HCS109K/Sample
HCS109HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
103
Spec Number 518748
File Number 2466.2

1 Page





HCS109D pdf, ピン配列
Specifications HCS109MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5 VCC (TR, TF) . . . . . . . .500ns Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Quiescent Current
SYMBOL
(NOTE 1)
CONDITIONS
ICC VCC = 5.5V,
VIN = VCC or GND
Output Current
(Sink)
IOL VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
IOH
VOL
VOH
IIN
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
VCC = 4.5V, VIH = 3.15V,
IOL = 50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
VCC = 5.5V, VIN = VCC or
GND
Noise Immunity
Functional Test
FN VCC = 4.5V,
VIH = 0.70(VCC),
VIL = 0.30(VCC) (Note 2)
GROUP
A SUB-
GROUPS
1
2, 3
1
2, 3
1
2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2, 3
7, 8A, 8B
TEMPERATURE
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC
+125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC
+125oC, -55oC
+25oC, +125oC, -55oC
NOTES:
1. All voltages reference to device GND.
2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
LIMITS
MIN MAX
- 20
- 400
4.8 -
4.0 -
-4.8 -
-4.0 -
- 0.1
- 0.1
VCC
-0.1
VCC
-0.1
-
-
-
-
-
±0.5
±5.0
-
UNITS
µA
µA
mA
mA
mA
mA
V
V
V
V
µA
µA
-
Spec Number 518748
105


3Pages


HCS109D 電子部品, 半導体
Specifications HCS109MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
Interim Test I (Postburn-In)
Interim Test II (Postburn-In)
PDA
Interim Test III (Postburn-In)
PDA
Final Test
Group A (Note 1)
Group B
Subgroup B-5
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
GROUP A SUBGROUPS
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Group D
Sample/5005
1, 7, 9
NOTES:
1. Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.
READ AND RECORD
ICC, IOL/H
ICC, IOL/H
ICC, IOL/H
ICC, IOL/H
Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE
GROUPS
METHOD
PRE RAD
Group E Subgroup 2
5005
1, 7, 9
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TEST
POST RAD
Table 4
READ AND RECORD
PRE RAD
POST RAD
1, 9 Table 4 (Note 1)
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
6, 7, 9, 10
1 - 5, 8, 11 - 15
-
16
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
6, 7, 9, 10
8
- 1 - 5, 11 - 16
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
8
6, 7, 9, 10
1, 5, 11, 15, 16
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in
OSCILLATOR
50kHz
25kHz
--
--
4, 12
2, 3, 13, 14
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
6, 7, 9, 10
8
1 - 5, 11 - 16
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518748
108

6 Page



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部品番号部品説明メーカ
HCS109D

Radiation Hardened Dual JK Flip Flop

Intersil Corporation
Intersil Corporation
HCS109DMSR

Radiation Hardened Dual JK Flip Flop

Intersil Corporation
Intersil Corporation
HCS109HMSR

Radiation Hardened Dual JK Flip Flop

Intersil Corporation
Intersil Corporation
HCS109K

Radiation Hardened Dual JK Flip Flop

Intersil Corporation
Intersil Corporation


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