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RTL8201EL-VB-GR の電気的特性と機能

RTL8201EL-VB-GRのメーカーはRealtekです、この部品の機能は「SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 RTL8201EL-VB-GR
部品説明 SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER
メーカ Realtek
ロゴ Realtek ロゴ 




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RTL8201EL-VB-GR Datasheet, RTL8201EL-VB-GR PDF,ピン配置, 機能
RTL8201E-GR
RTL8201EL-GR
RTL8201E-VB-GR
RTL8201EL-VB-GR
SINGLE-CHIP/PORT 10/100 FAST
ETHERNET PHYCEIVER WITH AUTO MDIX
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.3
16 December 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com

1 Page





RTL8201EL-VB-GR pdf, ピン配列
RTL8201E(L)
Datasheet
Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1
2. FEATURES .........................................................................................................................................................................2
3. APPLICATIONS ................................................................................................................................................................2
4. BLOCK DIAGRAM ...........................................................................................................................................................3
5. PIN ASSIGNMENTS .........................................................................................................................................................4
5.1. RTL8201EL LQFP-48 PIN ASSIGNMENTS...................................................................................................................4
5.2. GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................4
5.3. RTL8201E QFN-32 PIN ASSIGNMENTS.......................................................................................................................5
5.4. GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................5
6. PIN DESCRIPTIONS.........................................................................................................................................................6
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
MII INTERFACE............................................................................................................................................................6
RMII INTERFACE (RTL8201E(L)-VB ONLY)..............................................................................................................8
SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY ...................................................................................................8
CLOCK INTERFACE.......................................................................................................................................................8
10MBPS/100MBPS NETWORK INTERFACE ...................................................................................................................9
DEVICE CONFIGURATION INTERFACE ..........................................................................................................................9
LED INTERFACE/PHY ADDRESS CONFIGURATION ....................................................................................................10
POWER AND GROUND PINS ........................................................................................................................................10
RESET AND OTHER PINS.............................................................................................................................................10
NC (NOT CONNECTED) PINS ......................................................................................................................................10
7. REGISTER DESCRIPTIONS.........................................................................................................................................11
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
REGISTER 0 BASIC MODE CONTROL REGISTER..........................................................................................................11
REGISTER 1 BASIC MODE STATUS REGISTER.............................................................................................................12
REGISTER 2 PHY IDENTIFIER REGISTER 1..................................................................................................................12
REGISTER 3 PHY IDENTIFIER REGISTER 2..................................................................................................................13
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ...................................................................13
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) ....................................................14
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ............................................................................15
REGISTER 16 NWAY SETUP REGISTER (NSR)............................................................................................................15
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR).................................................15
REGISTER 18 RX_ER COUNTER (REC) .....................................................................................................................16
REGISTER 19 SNR DISPLAY REGISTER ......................................................................................................................16
REGISTER 25 TEST REGISTER.....................................................................................................................................16
8. FUNCTIONAL DESCRIPTION.....................................................................................................................................17
8.1. MII AND MANAGEMENT INTERFACE..........................................................................................................................18
8.1.1. Data Transition ....................................................................................................................................................18
8.1.2. Serial Management...............................................................................................................................................19
8.1.3. Interrupt (RTL8201EL-VB Only)..........................................................................................................................20
8.2. AUTO-NEGOTIATION AND PARALLEL DETECTION .....................................................................................................20
8.2.1. Setting the Medium Type and Interface Mode to MAC.........................................................................................20
8.3. FLOW CONTROL SUPPORT..........................................................................................................................................20
8.4. HARDWARE CONFIGURATION AND AUTO-NEGOTIATION...........................................................................................21
8.5. LED AND PHY ADDRESS CONFIGURATION ...............................................................................................................21
8.6. SERIAL NETWORK INTERFACE ...................................................................................................................................22
8.7. POWER DOWN, LINK DOWN, AND POWER SAVING MODES ........................................................................................22
8.8. MEDIA INTERFACE .....................................................................................................................................................23
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
iii
Track ID: JATR-1076-21 Rev. 1.3


3Pages


RTL8201EL-VB-GR 電子部品, 半導体
RTL8201E(L)
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................3
FIGURE 2. RTL8201EL LQFP-48 PIN ASSIGNMENTS....................................................................................................................4
FIGURE 3. RTL8201E QFN-32 PIN ASSIGNMENT..........................................................................................................................5
FIGURE 4. READ CYCLE...............................................................................................................................................................19
FIGURE 5. WRITE CYCLE .............................................................................................................................................................19
FIGURE 6. LED AND PHY ADDRESS CONFIGURATION ................................................................................................................21
FIGURE 7. POWER ON SEQUENCE ................................................................................................................................................26
FIGURE 8. PHY RESET SEQUENCE...............................................................................................................................................27
FIGURE 9. MII TRANSMISSION CYCLE TIMING-1.........................................................................................................................29
FIGURE 10. MII TRANSMISSION CYCLE TIMING-2.........................................................................................................................29
FIGURE 11. MII RECEPTION CYCLE TIMING-1 ..............................................................................................................................30
FIGURE 12. MII RECEPTION CYCLE TIMING-2 ..............................................................................................................................30
FIGURE 13. RMII TRANSMISSION CYCLE TIMING .........................................................................................................................31
FIGURE 14. RMII RECEPTION CYCLE TIMING ...............................................................................................................................31
FIGURE 15. SNI TRANSMISSION CYCLE TIMING-1 ........................................................................................................................32
FIGURE 16. SNI TRANSMISSION CYCLE TIMING-2 ........................................................................................................................32
FIGURE 17. SNI RECEPTION CYCLE TIMING-1 ..............................................................................................................................33
FIGURE 18. SNI RECEPTION CYCLE TIMING-2 ..............................................................................................................................33
FIGURE 19. MDC/MDIO TIMING..................................................................................................................................................34
FIGURE 20. MAC TO PHY TRANSMISSION WITHOUT COLLISION .................................................................................................34
FIGURE 21. PHY TO MAC RECEPTION WITHOUT ERROR .............................................................................................................35
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
vi
Track ID: JATR-1076-21 Rev. 1.3

6 Page



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部品番号部品説明メーカ
RTL8201EL-VB-GR

SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER

Realtek
Realtek


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