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25L3205D の電気的特性と機能

25L3205DのメーカーはMacronix Internationalです、この部品の機能は「MX25L3205D」です。


製品の詳細 ( Datasheet PDF )

部品番号 25L3205D
部品説明 MX25L3205D
メーカ Macronix International
ロゴ Macronix International ロゴ 




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25L3205D Datasheet, 25L3205D PDF,ピン配置, 機能
MX25L1605D
MX25L3205D
MX25L6405D
FEATURES
16M-BIT [x 1 / x 2] CMOS SERIAL FLASH
32M-BIT [x 1 / x 2] CMOS SERIAL FLASH
64M-BIT [x 1 / x 2] CMOS SERIAL FLASH
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure
32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure
64M:67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O read mode) structure
• 512 Equal Sectors with 4K byte each (16Mb)
1024 Equal Sectors with 4K byte each (32Mb)
2048 Equal Sectors with 4K byte each (64Mb)
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each (16Mb)
64 Equal Blocks with 64K byte each (32Mb)
128 Equal Blocks with 64K byte each (64Mb)
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)
- Serial clock of two I/O read mode : 50MHz (15pF + TTL Load), which is equivalent to 100MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 60ms(typ.) /sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip for
16Mb, 25s(typ.) for 32Mb, and 50s(typ.) for 64Mb
• Low Power Consumption
- Low active read current: 25mA(max.) at 86MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
- Deep power-down mode 1uA (typical)
• Typical 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1290
1 REV. 1.4, OCT. 01, 2008

1 Page





25L3205D pdf, ピン配列
MX25L1605D
MX25L3205D
MX25L6405D
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for more
details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.
The MX25L1605D/3205D/6405D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even
after typical 100,000 program and erase cycles.
Table 1. Additional Feature Comparison
Additional
Featu-
res
Part Name
Protection and Security
Flexible
Block
protection
(BP0-BP3)
512-bit
secured OTP
Read
Performance
2 I/O Read
(50MHz)
Device ID
(command :
AB hex)
MX25L1605D
V
V
V 14 (hex)
Identifier
Device ID
(command :
90 hex)
Device ID
(command :
EF hex)
RDID
(command:
9F hex)
C2 14 (hex)
(if ADD=0)
C2 14 (hex)
(if ADD=0) C2 20 15 (hex)
MX25L3205D
V
V
C2 15 (hex) C2 15 (hex)
V
15 (hex)
(if ADD=0)
(if ADD=0) C2 20 16 (hex)
MX25L6405D
V
V
C2 16 (hex) C2 16 (hex)
V
16 (hex)
(if ADD=0)
(if ADD=0) C2 20 17 (hex)
P/N: PM1290
REV. 1.4, OCT. 01, 2008
3


3Pages


25L3205D 電子部品, 半導体
MX25L1605D
MX25L3205D
MX25L6405D
DATA PROTECTION
The MX25L1605D/3205D/6405D is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transition. During power up the device automatically resets the
state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features to
prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and
tPUW (internal timer) may protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte
boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other
command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
- Write Read-lock Bit (WRLB) instruction completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing
all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command
(RES).
• Advanced Security Features: there are some protection and securuity features which protect content from inadvertent
write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read
only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible
which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) use WP#/ACC to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
P/N: PM1290
REV. 1.4, OCT. 01, 2008
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
25L3205

MX25L3205

Macronix International
Macronix International
25L3205D

MX25L3205D

Macronix International
Macronix International


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