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KSZ9031RNX の電気的特性と機能

KSZ9031RNXのメーカーはMicrel Semiconductorです、この部品の機能は「Gigabit Ethernet Transceiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 KSZ9031RNX
部品説明 Gigabit Ethernet Transceiver
メーカ Micrel Semiconductor
ロゴ Micrel Semiconductor ロゴ 




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KSZ9031RNX Datasheet, KSZ9031RNX PDF,ピン配置, 機能
KSZ9031RNX
Gigabit Ethernet Transceiver
with RGMII Support
Revision 2.2
General Description
The KSZ9031RNX is a completely integrated triple-speed
(10Base-T/100Base-TX/1000Base-T) Ethernet physical-
layer transceiver for transmission and reception of data on
standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9031RNX provides the reduced gigabit media
independent interface (RGMII) for direct connection to
RGMII MACs in gigabit Ethernet processors and switches
for data transfer at 10/100/1000Mbps.
The KSZ9031RNX reduces board cost and simplifies
board layout by using on-chip termination resistors for the
four differential pairs and by integrating an LDO controller
to drive a low-cost MOSFET to supply the 1.2V core.
The KSZ9031RNX offers diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ9031 I/Os and the
board. The LinkMD® TDR-based cable diagnostic identifies
faulty copper cabling. Remote and local loopback functions
verify analog and digital data paths.
The standard KSZ9031RNX is available in the 48-pin,
lead-free QFN package, and the AEC-Q100 automotive
qualified parts, KSZ9031RNXUA and KSZ9031RNXVA,
are available in the 48-pin lead-free WQFN package (see
Ordering Information).
Data sheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
Features
Single-chip 10/100/1000Mbps IEEE 802.3-compliant
Ethernet transceiver
RGMII timing supports on-chip delay according to
RGMII Version 2.0, with programming options for
external delay and making adjustments and corrections
to TX and RX timing paths
RGMII with 3.3V/2.5V/1.8V tolerant I/Os
Auto-negotiation to automatically select the highest link-
up speed (10/100/1000Mbps) and duplex (half/full)
On-chip termination resistors for the differential pairs
On-chip LDO controller to support single 3.3V supply
operation – requires only one external FET to generate
1.2V for the core
Jumbo frame support up to 16KB
125MHz reference clock output
Energy detect power-down mode for reduced power
consumption when the cable is not attached
Energy Efficient Ethernet (EEE) support with low-power
idle (LPI) mode and clock stoppage for 100Base-TX/
1000Base-T and transmit amplitude reduction with
10Base-Te option
Wake-On-LAN (WOL) support with robust custom-
packet detection
AEC-Q100 qualified for automotive applications
(KSZ9031RNXUA, KSZ9031RNXVA)
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 14, 2015
Revision 2.2

1 Page





KSZ9031RNX pdf, ピン配列
Micrel, Inc.
KSZ9031RNX
Revision History
Revision
1.0
Date
10/31/12
2.0 07/31/13
2.1 11/18/14
2.2 5/14/15
Summary of Changes
Data sheet created
Updated Functional Diagram with “PME_N” signal.
Indicated pin type is not an open-drain for PME_N1 (Pin 17) and INT_N/PME_N2 (Pin 38).
Deleted TSLP package height from Package Information(11) and Recommended Land Pattern.
Added typical series resistance and load capacitance for crystal selection criteria.
Added setup/hold timings for integrated delays per the RGMII v2.0 Specification.
Added note that RGMII data-to-clock skews for 10/100Mbps speeds are looser than for 1000Mbps
speed.
Corrected register definition for override strap-in for LED_MODE in MMD Address 2h, Register 0h.
Clarified register description for software power-down bit (Register 0h, Bit [11]).
Clarified power cycling specification to have all supply voltages to the KSZ9031RNX reach less
than 0.4V before the next power-up cycle.
Added AEC-Q100 automotive qualified part numbers, KSZ9031RNXUA and KSZ9031RNXVA, to
General Description, Features, Ordering Information and Electrical Characteristics(10) sections.
Added Package Information(11) and Recommended Land Pattern for 48-pin (7mm x 7mm)
WQFN for the automotive qualified part numbers.
Corrected Package Information(11) and Recommended Land Pattern for 48-pin (7mm x 7mm)
QFN. This is a datasheet correction. There is no change to the 48-pin (7mm x 7mm) QFN package.
Added note that internal pull-up values are measured with pin input voltage level at 1/2 DVDDH in
Electrical Characteristics(10) section.
Corrected datasheet revision 2.1 formatting errors for Standard Register 13h.
Added more details for XI (25MHz reference clock) input specification to Reference Clock –
Connection and Selection section.
Added note in Standard Register 0h, Bit [12] to indicate when Auto-Negotiation is disabled, Auto
MDI-X is also automatically disabled.
Added note in 10Base-T Receive section that all 7 bytes of preamble are removed.
Added instruction in Register 9h, Bits [15:13] to enable 1000Base-T Test Mode.
Added description in Auto-Negotiation Timing section to change FLP timing from 8ms to 16ms.
Added MMD Address 0h, Registers 3h and 4h for FLP timing.
Specified maximum frequency (minimum clock period) for MDC clock.
Updated input leakage current for the digital input pins in Electrical Characteristics(10) section.
Added minimum output currents for the digital output pins in Electrical Characteristics(10) section.
Corrected output drive current for LED1 and LED2 pins in Electrical Characteristics(10) section.
Updated Reset Circuit section and added reset circuit with MIC826 Voltage Supervisor.
Clarified LED indication support for 1.8V DVDDH requires voltage level shifters.
Added 10/100 Speeds Only section.
Added section for MOSFET selection for optional on-chip LDO controller.
Clarified RGMII timing and added Original RGMII (v1.3) timing with external delay for reference.
May 14, 2015
3 Revision 2.2


3Pages


KSZ9031RNX 電子部品, 半導体
Micrel, Inc.
KSZ9031RNX
List of Figures
Figure 1. KSZ9031RNX Block Diagram............................................................................................................................... 15
Figure 2. KSZ9031RNX 1000Base-T Transceiver Block Diagram – Single Channel.......................................................... 17
Figure 3. Auto-Negotiation Flow Chart................................................................................................................................. 20
Figure 4. KSZ9031RNX RGMII Interface............................................................................................................................. 23
Figure 5. Local (Digital) Loopback ....................................................................................................................................... 30
Figure 6. Remote (Analog) Loopback .................................................................................................................................. 31
Figure 7. LPI Mode (Refresh Transmissions and Quiet Periods) ........................................................................................ 34
Figure 8. LPI Transition – RGMII (1000Mbps) Transmit ...................................................................................................... 35
Figure 9. LPI Transition – RGMII (100Mbps) Transmit........................................................................................................ 36
Figure 10. LPI Transition – RGMII (1000Mbps) Receive..................................................................................................... 36
Figure 11. LPI Transition – RGMII (100Mbps) Receive ....................................................................................................... 37
Figure 12. RGMII v2.0 Spec (Figure 2 – Multiplexing and Timing Diagram – Original RGMII (v1.3) with external delay) ... 69
Figure 13. RGMII v2.0 Spec (Figure 3 – Multiplexing and Timing Diagram – RGMII-ID (v2.0) with internal chip delay) ..... 70
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 72
Figure 15. MDC/MDIO Timing............................................................................................................................................... 73
Figure 16. Power-Up/Power-Down/Reset Timing ................................................................................................................. 74
Figure 17. Reset Circuit for Triggering by Power Supply...................................................................................................... 75
Figure 18. Reset Circuit for Interfacing with CPU/FPGA Reset Output ................................................................................ 75
Figure 19. Rest Circuit with MIC826 Voltage Supervisor...................................................................................................... 76
Figure 20. Reference Circuits for LED Strapping Pins ......................................................................................................... 76
Figure 21. 25MHz Crystal/Oscillator Reference Clock Connection ...................................................................................... 77
Figure 22. Typical Gigabit Magnetic Interface Circuit ........................................................................................................... 78
May 14, 2015
6 Revision 2.2

6 Page



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部品番号部品説明メーカ
KSZ9031RNX

Gigabit Ethernet Transceiver

Micrel Semiconductor
Micrel Semiconductor
KSZ9031RNX

Gigabit Ethernet Transceiver

Micrel Semiconductor
Micrel Semiconductor


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