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PDF HCPL-M601 Data sheet ( Hoja de datos )
| Número de pieza | HCPL-M601 | |
| Descripción | Small Outline/ 5 Lead/ High CMR/ High Speed/ Logic Gate Optocouplers | |
| Fabricantes | Agilent(Hewlett-Packard) | |
| Logotipo | .gif "Agilent(Hewlett-Packard)"){kind=logo} |
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Small Outline, 5 Lead, High
CMR, High Speed, Logic Gate
Optocouplers
Technical Data
HCPL-M600
HCPL-M601
HCPL-M611
Features
• Surface Mountable
• Very Small, Low Profile
JEDEC Registered Package
Outline
• Compatible with Infrared
Vapor Phase Reflow and
Wave Soldering Processes
• Internal Shield for High
Common Mode Rejection
(CMR)
HCPL-M601: 10,000 V/µs at
VCM = 50 V
HCPL-M611: 15,000 V/µs at
VCM = 1000 V
• High Speed: 10 Mbd
• LSTTL/TTL Compatible
• Low Input Current
Capability: 5 mA
• Guaranteed ac and dc
Performanceover
Temperature: -40°C to 85°C
• Recognized under the
Component Program of U.L.
(File No. E55361) for
Dielectric Withstand Proof
Test Voltage of 2500 Vac, 1
Minute
Description
These small outline high CMR,
high speed, logic gate optocoup-
lers are single channel devices in
a five lead miniature footprint.
They are electrically equivalent to
the following Agilent
optocouplers (except there is no
output enable feature):
SO-5 Package
HCPL-M600
HCPL-M601
HCPL-M611
Standard DIP
6N137
HCPL-2601
HCPL-2611
SO-8 Package
HCPL-0600
HCPL-0601
HCPL-0611
The SO-5 JEDEC registered (MO-
155) package outline does not
require “through holes” in a PCB.
This package occupies
approximately one fourth the
footprint area of the standard
dual-in-line package. The lead
profile is designed to be com-
patible with standard surface
mount processes.
The HCPL-M600/01/11 optically
coupled gates combine a GaAsP
light emitting diode and an
integrated high gain photon
detector. The output of the
detector I.C. is an Open-collector
Schottky-clamped transistor. The
internal shield provides a
guaranteed common mode
transient immunity specification of
5,000 V/µs for the HCPL-M601,
and 10,000 V/µs for the HCPL-
M611.
This unique design provides
maximum ac and dc circuit
isolation while achieving TTL
compatibility. The optocoupler ac
and dc operational parameters are
guaranteed from -40°C to 85°C
allowing trouble free system
performance.
CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken
in handling and assembly of this component to prevent damage and/or degradation which may be induced by
ESD.
1 page  
5
Switching Specifications
Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
Device
Parameter Symbol HCPL- Min. Typ.* Max. Unit
Test Conditions Fig. Note
Propagation
Delay Time
to High
Output Level
tPLH
20 48 75 ns TA = 25°C
100
6, 7 5
8
Propagation
Delay Time
to Low
Output Level
tPHL
25 50 75
100
TA = 25°C
RL = 350 Ω
6, 7 6
8
Propagation
Delay Skew
tPSK
40
10,
11
Pulse Width |tPHL - tPLH|
Distortion
3.5 35
CL = 15 pF
9 10
Output Rise
Time
(10%-90%)
trise
24
10
Output Fall
Time
(10%-90%)
tfall
10
10
Common
Mode
Transient
Immunity at
High Output
Level
|CMH|
M600
10,000
M601 5,000 10,000
M611 10,000 15,000
V/µs
VCM = 10 V VO(min) = 2 V
VCM = 50 V
RL = 350 Ω
IF = 0 mA
VCM = 1000 V TA = 25°C
11 7, 9
Common
Mode
Transient
Immunity at
Low Output
Level
|CMH|
M600
10,000
M601 5,000 10,000
M611 10,000 15,000
VCM = 10 V VO(max) = 0.8 V
VCM = 50 V
RL = 350 Ω
IF = 7.5 mA
VCM = 1000 V TA = 25°C
11
8, 9
*All typicals at TA = 25°C, VCC = 5 V.
Notes:
1. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler. The total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 20 mA.
3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 VRMS for 1 second
(Leakage detection current limit, II-O ≤ 5 µA).
5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., VOUT > 2.0 V).
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., VOUT > 0.8 V).
9. For sinusoidal voltages, (|dVCM|/dt)max = πfCMVCM(p-p).
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the worst case operating condition range.
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HCPL-M601.PDF ] | |
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