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IS46R86400D の電気的特性と機能

IS46R86400DのメーカーはIntegrated Silicon Solutionです、この部品の機能は「16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS46R86400D
部品説明 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS46R86400D Datasheet, IS46R86400D PDF,ピン配置, 機能
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
16Mx32, 32Mx16, 64Mx8 NOVEMBER 2012
512Mb DDR SDRAM
FEATURES
• VDD and VDDQ: 2.5V ± 0.2V (-6)
• VDD and VDDQ: 2.6V ± 0.1V (-5)
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers
per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
• DQS is edge-aligned with data for READs and
centre-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
• Four internal banks for concurrent operation
• Data Mask for write data. DM masks write data
at both rising and falling edges of data strobe
• Burst Length: 2, 4 and 8
• Burst Type: Sequential and Interleave mode
• Programmable CAS latency: 2, 2.5 and 3
• Auto Refresh and Self Refresh Modes
• Auto Precharge
• TRAS Lockout Supported (tRAP = tRCD )
OPTIONS
• Configuration(s): 16Mx32, 32Mx16, and 64Mx8
• Package(s): 144 Ball BGA (x32), 66-pin TSOP-II
(x8, x16), and 60 Ball BGA (x8, x16)
• Lead-free package
• Temperature Range:
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Automotive, A1 (-40°C to +85°C)
Automotive, A2 (-40°C to +105°C)
DEVICE OVERVIEW
ISSI’s 512-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 536,870,912-bit memory
array is internally organized as four banks of 128Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 8-bit, 16-bit and 32-bit data word size
Input data is registered on the I/O pins on both edges
of Data Strobe signal(s), while output data is referenced
to both edges of Data Strobe and both edges of CLK.
Commands are registered on the positive edges of CLK.
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.
ADDRESS TABLE
Parameter 16M x 32
Configuration 4M x 32 x 4
banks
Bank Address BA0, BA1
Pins
Autoprecharge A8/AP
Pins
Row Address 8K(A0 – A12)
Column
Address
512(A0 – A7,
A9)
Refresh Count
Com./Ind./A1 8K / 64ms
A2 8K / 16ms
32M x 16
8M x 16 x 4
banks
BA0, BA1
A10/AP
8K(A0 – A12)
1K(A0 – A9)
8K / 64ms
8K / 16ms
64M x 8
16M x 8 x 4
banks
BA0, BA1
A10/AP
8K(A0 – A12)
2K(A0 – A9,
A11)
8K / 64ms
8K / 16ms
KEY TIMING PARAMETERS
Speed Grade
-5 -6
Fck Max CL = 3 200 167
Fck Max CL = 2.5 167 167
Fck Max CL = 2 133 133
Units
MHz
MHz
MHz
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can rea-
sonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. 1
Rev.C
11/20/2012

1 Page





IS46R86400D pdf, ピン配列
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
FUNCTIONAL BLOCK DIAGRAM (x16)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
Mode Registers and
Ext. Mode Registers
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
15
ROW
ADDRESS
13 LATCH
13
COLUMN
ADDRESS LATCH
10
BURST COUNTER
COLUMN
ADDRESS BUFFER
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
DATA IN
BUFFER
16
16
LDM, UDM
2
I/O 0-15
2 LDQS, UDQS
DATA OUT
BUFFER
16 16
VDD/VDDQ
Vss/VssQ
REFRESH
COUNTER
13
2
ROW
ADDRESS
BUFFER
13
13
8192
8192
8192
8192
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
2 1024
(x 16)
BANK CONTROL LOGIC
COLUMN DECODER
10
Integrated Silicon Solution, Inc.
Rev. C
11/20/2012
3


3Pages


IS46R86400D 電子部品, 半導体
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PIN DESCRIPTION: x16
A0-A12
Row Address Input
A0-A9
Column Address Input
BA0, BA1
Bank Select Address
DQ0 – DQ15
Data I/O
CK, CK
System Clock Input
CKE
Clock Enable
CS Chip Select
CAS
Column Address Strobe
Command
RAS
Row Address Strobe
Command
WE Write Enable
6
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
LDM, UDM
LDQS, UDQS
VDD
VDDQ
VSS
VSSQ
VREF
NC
Data Write Mask
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
Integrated Silicon Solution, Inc.
Rev. C
11/20/2012

6 Page



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部品番号部品説明メーカ
IS46R86400D

16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM

Integrated Silicon Solution
Integrated Silicon Solution


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