DataSheet.jp

AT45DB161E-CCUD-T の電気的特性と機能

AT45DB161E-CCUD-TのメーカーはATMEL Corporationです、この部品の機能は「2.3V or 2.5V Minimum SPI Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT45DB161E-CCUD-T
部品説明 2.3V or 2.5V Minimum SPI Serial Flash Memory
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 




このページの下部にプレビューとAT45DB161E-CCUD-Tダウンロード(pdfファイル)リンクがあります。

Total 70 pages

No Preview Available !

AT45DB161E-CCUD-T Datasheet, AT45DB161E-CCUD-T PDF,ピン配置, 機能
Atmel AT45DB161E
16-Mbits DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum
SPI Serial Flash Memory
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V or 2.5V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports Atmel® RapidSoperation
Continuous Read capability through entire array
Up to 85MHz
Low-power Read option up to 10MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
512 bytes per page
528 bytes per page (default)
Page size can be factory pre-configured for 512 bytes
Two fully independent SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the Main Memory Array
Flexible programming options
Byte/Page program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible Erase options
Page Erase (512/528 bytes)
Block Erase (4KB)
Sector Erase (128KB)
Chip Erase (16-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
500nA Ultra-Deep Power-Down current (typical)
3μA Deep Power-Down current (typical)
25μA Standby current (typical)
11mA Active Read current (typical)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Chip-scale BGA (5 x 5 x 1.2mm)
8782A–DFLASH–3/12

1 Page





AT45DB161E-CCUD-T pdf, ピン配列
Table 1-1. Pin Configurations
Symbol
CS
SCK
SI
SO
WP
RESET
VCC
GND
Name and Function
Asserted
State
Type
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in the standby mode (not Deep Power-Down
mode) and the output pin (SO) will be in a high-impedance state. When the device is
deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such
as a program or erase cycle, the device will not enter the standby mode until the completion of
the operation.
Low
Input
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is
always latched on the rising edge of SCK, while output data on the SO pin is always clocked
out on the falling edge of SCK.
Input
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected
(CS is deasserted).
Input
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state
whenever the device is deselected (CS is deasserted).
— Output
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector
Protection Register will be protected against program and erase operations regardless of
whether the Enable Sector Protection command has been issued or not. The WP pin functions
independently of the software controlled protection method. After the WP pin goes low, the
content of the Sector Protection Register can not be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the device
will simply ignore the command and perform no operation. The device will return to the idle
state once the CS pin has been deasserted. The Enable Sector Protection command and
Sector Lockdown command, however, will be recognized by the device when the WP pin is
asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected to
VCC whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long
as a low level is present on the RESET pin. Normal operation can resume once the RESET
pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and features are not utilized it is
recommended that the RESET pin be driven high externally.
Low
Low
Input
Input
Device Power Supply: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
Power
Ground: The ground reference for the power supply. GND should be connected to the system
ground.
— Ground
Atmel AT45DB161E [PRELIMINARY DATASHEET]
8782A–DFLASH–3/12
3


3Pages


AT45DB161E-CCUD-T 電子部品, 半導体
4. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated
opcodes are contained in Table 15-1 on page 40 through Table 15-4 on page 41. A valid instruction starts with the falling
edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the
CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address
location through the SI (Serial Input) pin. All instructions, addresses, and data are transferred with the Most Significant Bit
(MSB) first.
Buffer addressing for the standard DataFlash page size (528 bytes) is referenced in the datasheet using the terminology
BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer. The main memory
addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0, where PA11 - PA0 denotes the 12 address
bits required to designate a page address, and BA9 - BA0 denotes the 10 address bits required to designate a byte
address within the page.
For the "Power of 2" binary page size (512 bytes), the buffer addressing is referenced in the datasheet using the
conventional terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a
buffer. Main memory addressing is referenced using the terminology A20 - A0, where A20 - A9 denotes the 12 address
bits required to designate a page address, and A8 - A0 denotes the nine address bits required to designate a byte
address within a page.
Atmel AT45DB161E [PRELIMINARY DATASHEET]
8782A–DFLASH–3/12
6

6 Page



ページ 合計 : 70 ページ
 
PDF
ダウンロード
[ AT45DB161E-CCUD-T データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
AT45DB161E-CCUD-T

2.3V or 2.5V Minimum SPI Serial Flash Memory

ATMEL Corporation
ATMEL Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap