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AT45DB041D-MU-SL954 の電気的特性と機能

AT45DB041D-MU-SL954のメーカーはAdestoです、この部品の機能は「4-megabit 2.5-volt or 2.7-volt DataFlash」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT45DB041D-MU-SL954
部品説明 4-megabit 2.5-volt or 2.7-volt DataFlash
メーカ Adesto
ロゴ Adesto ロゴ 




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AT45DB041D-MU-SL954 Datasheet, AT45DB041D-MU-SL954 PDF,ピン配置, 機能
Features
Single 2.5V or 2.7V to 3.6V Supply
RapidSTM Serial Interface: 66MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 256-Bytes per Page
– 264-Bytes per Page
– Page Size Can Be Factory Pre-configured for 256-Bytes
Page Program Operation
– Intelligent Programming Operation
– 2,048 Pages (256-/264-Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256-Bytes)
– Block Erase (2-Kbytes)
– Sector Erase (64-Kbytes)
– Chip Erase (4Mbits)
Two SRAM Data Buffers (256-, 264-Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7mA Active Read Current Typical
– 25μA Standby Current Typical
– 15μA Deep Power-down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
4-megabit
2.5-volt or
2.7-volt
DataFlash®
AT45DB041D
(Not recommended for
new designs. Use
AT45DB041E.)
1. Description
The AT45DB041D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB041D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66MHz. Its 4,325,376-bits of memory are organized as 2,048 pages of 256-bytes or
264-bytes each. In addition to the main memory, the AT45DB041D also contains two
SRAM buffers of 256-/264-bytes each. The buffers allow the receiving of data while a
page in the main Memory is being reprogrammed, as well as writing a continuous data
stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-con-
tained three step read-modify-write operation. Unlike conventional Flash memories
that are accessed randomly with multiple address lines and a parallel interface, the
DataFlash uses a RapidS serial interface to sequentially access its data. The simple
sequential access dramatically
3595T–DFLASH–8/2013

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AT45DB041D-MU-SL954 pdf, ピン配列
AT45DB041D
Figure 2-1. MLF (VDFN)Top View
SI 1
SCK 2
RESET 3
CS 4
8 SO
7 GND
6 VCC
5 WP
Figure 2-2. SOIC Top View
SI
SCK
RESET
CS
1
2
3
4
8 SO
7 GND
6 VCC
5 WP
Note: 1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND
3. Block Diagram
WP FLASH MEMORY ARRAY
PAGE (256-/264-BYTES)
SCK
CS
RESET
VCC
GND
BUFFER 1 (256-/264-BYTES)
BUFFER 2 (256-/264-BYTES)
I/O INTERFACE
SI SO
3595T–DFLASH–8/2013
3


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AT45DB041D-MU-SL954 電子部品, 半導体
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous
Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both
data buffers and leaves the contents of the buffers unchanged.
6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33MHz
This command can be used with the serial interface to read the main memory array sequentially
without a dummy byte up to maximum frequencies specified by fCAR2. To perform a continuous
read array with the page size set to 264-bytes, the CS must first be asserted then an opcode,
03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence). The first 11 bits (PA10 - PA0) of the 20-bit address sequence
specify which page of the main memory array to read, and the last nine bits (BA8 - BA0) of the
20-bit address sequence specify the starting byte address within the page. To perform a contin-
uous read with the page size set to 256-bytes, the opcode, 03H, must be clocked into the device
followed by three address bytes (A18 - A0). Following the address bytes, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and
leaves the contents of the buffers unchanged.
6.4 Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 2,048 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the DataFlash standard page size (264-bytes), an opcode
of D2H must be clocked into the device followed by three address bytes (which comprise the
24-bit page and byte address sequence) and four don’t care bytes. The first 11 bits (PA10 -
PA0) of the 20-bit address sequence specify the page in main memory to be read, and the last
nine bits (BA8 - BA0) of the 20-bit address sequence specify the starting byte address within
that page. To start a page read from the binary page size (256-bytes), the opcode D2H must be
clocked into the device followed by three address bytes and four don’t care bytes. The first 11
bits (A18 - A8) of the 19-bits sequence specify which page of the main memory array to read,
and the last 8 bits (A7 - A0) of the 19-bits address sequence specify the starting byte address
within the page. The don’t care bytes that follow the address bytes are sent to initialize the read
operation. Following the don’t care bytes, additional pulses on SCK result in data being output
on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data. When the end of a page in main
6 AT45DB041D
3595T–DFLASH–8/2013

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共有リンク

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部品番号部品説明メーカ
AT45DB041D-MU-SL954

4-megabit 2.5-volt or 2.7-volt DataFlash

Adesto
Adesto
AT45DB041D-MU-SL955

4-megabit 2.5-volt or 2.7-volt DataFlash

Adesto
Adesto


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