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AT25SF081-SSHD-T の電気的特性と機能

AT25SF081-SSHD-TのメーカーはAdestoです、この部品の機能は「2.5V Minimum SPI Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT25SF081-SSHD-T
部品説明 2.5V Minimum SPI Serial Flash Memory
メーカ Adesto
ロゴ Adesto ロゴ 




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AT25SF081-SSHD-T Datasheet, AT25SF081-SSHD-T PDF,ピン配置, 機能
AT25SF081
8-Mbit, 2.5V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-IO Support
Features
PRELIMINARY DATASHEET
Single 2.5V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual and Quad Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Blocks via WP Pin
3 Protected Programmable Security Register Pages
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
0.7ms Typical Page Program (256 Bytes) Time
70ms Typical 4-Kbyte Block Erase Time
300ms Typical 32-Kbyte Block Erase Time
600ms Typical 64-Kbyte Block Erase Time
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
4mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil and 208-mil)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm) (1)
8-lead TSSOP (4 x 4 mm)(1)
1. TSSOP and DFN packages are not currently in production. Package outline dimensions are subject
to change.
DS-25SF081A–045B–5/2014

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AT25SF081-SSHD-T pdf, ピン配列
Table 1-1. Pin Descriptions (Continued)
Symbol Name and Function
Asserted
State
Type
SO (I/O1)
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in
conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every
falling edge of SCK
To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it will be
referenced as I/O1
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
- Input/Output
WP
(I/O2)
HOLD
(I/O3)
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please
refer to “Program/Erase Suspend (75h)” on page 17 for more details on protection features
and the WP pin.
With the Quad-Input Byte/Page Program command, the WP pin becomes an input pin (I/O2)
and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every rising
edge of SCK. With the Quad-Output Read commands, the WP Pin becomes an output pin
(I/O2) in conjunction with other pins to allow four bits of data on (I/O33-0) to be clocked in on
every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the WP (I/O2) pin will be referenced as
the WP pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O2
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold Function” on page 31 for additional details on the Hold operation.
With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin
(I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every
rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin becomes an
output pin (I/O3) in conjunction with other pins to allow four bits of data on (I/O33-0) to be
clocked in on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin will be referenced
as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O3
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to VCC
whenever possible.
- Input/Output
- Input/Output
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
VCC Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
-
Power
GND
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
- Power
AT25SF081
DS-25SF081A–045B–5/2014
3


3Pages


AT25SF081-SSHD-T 電子部品, 半導体
4. Device Operation
The AT25SF081 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25SF081 via the SPI bus which is comprised of four signal lines: Chip
Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25SF081
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 4-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
4.1 Dual Output Read
The AT25SF081 features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of
data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.
4.2 Quad Output Read
The AT25SF081 features a Quad-Output Read mode that allow four bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, the SI, SO, WP, HOLD pins are utilized as outputs for the transfer
of data bytes. With the Quad-Output Read Array command, the SI, WP, HOLD pins become outputs along with the SO
pin.
5. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25SF081 will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25SF081 memory array is 0FFFFFh, address bits A23-A19 are always ignored by
the device.
AT25SF081
DS-25SF081A–045B–5/2014
6

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部品番号部品説明メーカ
AT25SF081-SSHD-B

2.5V Minimum SPI Serial Flash Memory

Adesto
Adesto
AT25SF081-SSHD-T

2.5V Minimum SPI Serial Flash Memory

Adesto
Adesto


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