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AT25DN256 の電気的特性と機能

AT25DN256のメーカーはAdestoです、この部品の機能は「2.3V Minimum SPI Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT25DN256
部品説明 2.3V Minimum SPI Serial Flash Memory
メーカ Adesto
ロゴ Adesto ロゴ 




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AT25DN256 Datasheet, AT25DN256 PDF,ピン配置, 機能
AT25DN256
256-Kbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-Read Support
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
40ms Typical 4-Kbyte Block Erase Time
320ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
350nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
6mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6mm)
8-lead TSSOP Package
DS-25DN256–039B–5/2014

1 Page





AT25DN256 pdf, ピン配列
Table 2-1. Pin Descriptions (Continued)
Symbol
WP
HOLD
VCC
GND
Name and Function
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer
to “Protection Commands and Features” on page 12 for more details on protection features and
the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to VCC
whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold” on page 26 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to VCC whenever
possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
GROUND: The ground reference for the power supply. GND should be connected to the system
ground.
Asserted
State
Low
Low
-
-
Type
Input
Input
Power
Power
Table 2-2. Pinouts
Figure 2-1. 8-SOIC Top View
Figure 2-3. 8-UDFN (Top View)
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
Figure 2-2. 8-TSSOP Top View
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
AT25DN256
DS-25DN256–039B–5/2014
3


3Pages


AT25DN256 電子部品, 半導体
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25DN256 will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the 256 memory array is 00FFFFh, address bits A23-A16 are always ignored by the
device.
Table 6-1. Command Listing
Command
Read Commands
Read Array
Dual Output Read
Program and Erase Commands
Page Erase
Block Erase (4 Kbytes)
Block Erase (32 Kbytes)
Chip Erase
Chip Erase (Legacy Command)
Byte/Page Program (1 to 256 Bytes)
Protection Commands
Write Enable
Write Disable
Security Commands
Program OTP Security Register
Read OTP Security Register
Status Register Commands
Read Status Register
Write Status Register Byte 1
Opcode
Clock
Frequency
Address Dummy
Bytes
Bytes
Data
Bytes
0Bh 0000 1011 Up to 104MHz
03h 0000 0011 Up to 33MHz
3Bh 0011 1011 Up to 50MHz
3
3
3
1 1+
0 1+
1 1+
81h 1000 0001 Up to 104MHz
20h 0010 0000 Up to 104MHz
52h 0101 0010 Up to 104MHz
D8h 1101 1000 Up to 104MHz
60h 0110 0000 Up to 104MHz
C7h 1100 0111 Up to 104MHz
62h 0110 0010 Up to 104MHz
02h 0000 0010 Up to 104MHz
3
3
3
3
0
0
0
3
00
00
00
00
00
00
00
0 1+
06h 0000 0110 Up to 104MHz
0
0
0
04h 0000 0100 Up to 104MHz
0
0
0
9Bh 1001 1011 Up to 104MHz
77h 0111 0111 Up to 104MHz
3
3
0 1+
2 1+
05h 0000 0101 Up to 104MHz
01h 0000 0001 Up to 104MHz
0
0
0 1+
01
AT25DN256
DS-25DN256–039B–5/2014
6

6 Page



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共有リンク

Link :


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