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AT25DF512C-XMHNGU-T の電気的特性と機能

AT25DF512C-XMHNGU-TのメーカーはAdestoです、この部品の機能は「SPI Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT25DF512C-XMHNGU-T
部品説明 SPI Serial Flash Memory
メーカ Adesto
ロゴ Adesto ロゴ 




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AT25DF512C-XMHNGU-T Datasheet, AT25DF512C-XMHNGU-T PDF,ピン配置, 機能
AT25DF512C
512-Kbit, 1.65V Minimum
SPI Serial Flash Memory with Dual-I/O Support
Features
PRELIMINARY DATASHEET
Single 1.65V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
85MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
50ms Typical 4-Kbyte Block Erase Time
400ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
200nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
5mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Temperature Range:-10°C to +85°C (1.65V to 3.6V), -40°C to +85° (1.7V to 3.6V)
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
8-lead TSSOP Package
DS-25DF512C–030A–4/2014

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AT25DF512C-XMHNGU-T pdf, ピン配列
Table 2-1. Pin Descriptions (Continued)
Symbol Name and Function
Asserted
State
Type
SO (I/O1)
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O1) in
conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked out on every
falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it will be
referenced as I/O1.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
- Input/Output
WP
HOLD
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please
refer to “Protection Commands and Features” on page 12 for more details on protection
features and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a
Hold condition to start. A Hold condition pauses serial communication only and does
not have an effect on internally self-timed operations such as a program or erase cycle.
Please refer to “Hold” on page 27 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to VCC
whenever possible.
Low
Low
Input
Input
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
VCC Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
-
Power
GND
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
- Power
AT25DF512C
DS-25DF512C–030A–4/2014
3


3Pages


AT25DF512C-XMHNGU-T 電子部品, 半導体
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
5.1 Dual Output Read
The ATx features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every clock cycle
to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of data bytes.
With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25DF512C will be ignored by the device and no operation will be started. The device
will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25DF512C memory array is 00FFFFh, address bits A23-A16 are always ignored
by the device.
Table 6-1. Command Listing
Command
Read Commands
Read Array
Dual Output Read
Program and Erase Commands
Page Erase
Block Erase (4 Kbytes)
Block Erase (32 Kbytes)
Opcode
Clock
Frequency
Address Dummy
Bytes
Bytes
Data
Bytes
0Bh 0000 1011 Up to 85 MHz
03h 0000 0011 Up to 33 MHz (1)
3Bh 0011 1011 Up to 50 MHz
3
3
3
1 1+
0 1+
1 1+
81h 1000 0001 Up to 85 MHz
3
0
0
20h 0010 0000 Up to 85 MHz
3
0
0
52h 0101 0010 Up to 85 MHz
3
0
0
D8h 1101 1000 Up to 85 MHz
3
0
0
AT25DF512C
DS-25DF512C–030A–4/2014
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
AT25DF512C-XMHNGU-B

SPI Serial Flash Memory

Adesto
Adesto
AT25DF512C-XMHNGU-T

SPI Serial Flash Memory

Adesto
Adesto


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