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AT25DF321A の電気的特性と機能

AT25DF321AのメーカーはATMEL Corporationです、この部品の機能は「32-Megabit 2.7-volt MinimumSPI Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT25DF321A
部品説明 32-Megabit 2.7-volt MinimumSPI Serial Flash Memory
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 




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AT25DF321A Datasheet, AT25DF321A PDF,ピン配置, 機能
Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS® Operation
– Supports Dual-Input Program and Dual-Output Read
Very High Operating Frequencies
– 100 MHz for RapidS
– 85 MHz for SPI
– Clock-to-Output (tV) of 5 ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– 64 Sectors of 64-Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
– 1.0 ms Typical Page Program (256 Bytes) Time
– 50 ms Typical 4-Kbyte Block Erase Time
– 250 ms Typical 32-Kbyte Block Erase Time
– 400 ms Typical 64-Kbyte Block Erase Time
Program and Erase Suspend/Resume
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 5 mA Active Read Current (Typical at 20 MHz)
– 5 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
32-Megabit
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25DF321A
Preliminary
1. Description
The AT25DF321A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DF321A, with its erase granularity as small as
4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
3686C–DFLASH–12/08

1 Page





AT25DF321A pdf, ピン配列
AT25DF321A [Preliminary]
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol
CS
SCK
SI (SIO)
SO (SOI)
WP
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted,
the device will be deselected and normally be placed in standby mode (not Deep Power-
Down mode), and the SO pin will be in a high-impedance state. When the device is
deselected, data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
SERIAL INPUT (SERIAL INPUT/OUTPUT): The SI pin is used to shift data into the device.
The SI pin is used for all data input including command and address sequences. Data on the
SI pin is always latched in on the rising edge of SCK.
With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow
two bits of data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To
maintain consistency with SPI nomenclature, the SIO pin will be referenced as SI throughout
the document with exception to sections dealing with the Dual-Output Read Array command
in which it will be referenced as SIO.
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
SERIAL OUTPUT (SERIAL OUTPUT/INPUT): The SO pin is used to shift data out from the
device. Data on the SO pin is always clocked out on the falling edge of SCK.
With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI)
to allow two bits of data (on the SOI and SI pins) to be clocked in on every rising edge of
SCK. To maintain consistency with SPI nomenclature, the SOI pin will be referenced as SO
throughout the document with exception to sections dealing with the Dual-Input Byte/Page
Program command in which it will be referenced as SOI.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please
refer to “Protection Commands and Features” on page 21 for more details on protection
features and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
Asserted
State
Type
Low Input
- Input
- Input/Output
- Output/Input
Low Input
3686C–DFLASH–12/08
3


3Pages


AT25DF321A 電子部品, 半導体
Figure 4-1. Memory Architecture Diagram
6 AT25DF321A [Preliminary]
3686C–DFLASH–12/08

6 Page



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共有リンク

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