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PDF AT25DF321A-MH-Y Data sheet ( Hoja de datos )
| Número de pieza | AT25DF321A-MH-Y | |
| Descripción | 32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory | |
| Fabricantes | Adesto | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS Operation
– Supports Dual-Input Program and Dual-Output Read
• Very High Operating Frequencies
– 100MHz for RapidS
– 85MHz for SPI
– Clock-to-Output (tV) of 5ns Maximum
• Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature
– 64 Sectors of 64-Kbytes Each
• Hardware Controlled Locking of Protected Sectors via WP Pin
• Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
• 128-Byte Programmable OTP Security Register
• Flexible Programming
– Byte/Page Program (1- to 256-Bytes)
• Fast Program and Erase Times
– 1.0ms Typical Page Program (256-Bytes) Time
– 50ms Typical 4-Kbyte Block Erase Time
– 250ms Typical 32-Kbyte Block Erase Time
– 400ms Typical 64-Kbyte Block Erase Time
• Program and Erase Suspend/Resume
• Automatic Checking and Reporting of Erase/Program Failures
• Software Controlled Reset
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 12mA Active Read Current (Typical at 20MHz)
– 5µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)
– 9-ball UBGA (6 x 6 x 0.6 mm body - 1 mm pitch)
32-Mbit
2.7V Minimum
Serial Peripheral
Interface Serial
Flash Memory
AT25DF321A
3686F–DFLASH–1/2014
1 page  
Figure 4-1. Memory Architecture Diagram
AT25DF321A
3686F–DFLASH–1/2014
5
5 Page 
AT25DF321A
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to determine if the data
bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will
be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
Figure 8-1. Byte Program
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN
0 0 0 0 0 0 1 0AAAAAA
MSB
MSB
AAADDDDDDDD
MSB
SO HIGH-IMPEDANCE
Figure 8-2. Page Program
CS
SCK
SI
0123456789
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN BYTE 1
0 0 0 0 0 0 1 0AAA
MSB
MSB
AAADDDDDDDD
MSB
DATA IN BYTE n
DDDDDDDD
MSB
SO HIGH-IMPEDANCE
8.2 Dual-Input Byte/Page Program
The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be used to
program anywhere from a single byte of data up to 256-bytes of data into previously erased memory locations. Unlike the
standard Byte/Page Program command, however, the Dual-Input Byte/Page Program command allows two bits of data to be
clocked into the device on every clock cycle rather than just one.
Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been previously
issued to the device (see “Write Enable” on page 18) to set the Write Enable Latch (WEL) bit of the Status Register to a logical
“1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h must be clocked into the device followed
by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address
bytes have been clocked in, data can then be clocked into the device two bits at a time on both the SOI and SI pins.
The data is always input with the MSB of a byte first, and the MSB is always input on the SOI pin. During the first clock cycle,
bit 7 of the first data byte would be input on the SOI pin while bit 6 of the same data byte would be input on the SI pin. During
the next clock cycle, bits 5 and 4 of the first data byte would be input on the SOI and SI pins, respectively. The sequence would
continue with each byte of data being input after every four clock cycles. Like the standard Byte/Page Program command, all
data clocked into the device is stored in an internal buffer.
3686F–DFLASH–1/2014
11
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