DataSheet.jp

AT25DF321A-MH-T の電気的特性と機能

AT25DF321A-MH-TのメーカーはAdestoです、この部品の機能は「32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT25DF321A-MH-T
部品説明 32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
メーカ Adesto
ロゴ Adesto ロゴ 




このページの下部にプレビューとAT25DF321A-MH-Tダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

AT25DF321A-MH-T Datasheet, AT25DF321A-MH-T PDF,ピン配置, 機能
Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS Operation
– Supports Dual-Input Program and Dual-Output Read
Very High Operating Frequencies
– 100MHz for RapidS
– 85MHz for SPI
– Clock-to-Output (tV) of 5ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– 64 Sectors of 64-Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1- to 256-Bytes)
Fast Program and Erase Times
– 1.0ms Typical Page Program (256-Bytes) Time
– 50ms Typical 4-Kbyte Block Erase Time
– 250ms Typical 32-Kbyte Block Erase Time
– 400ms Typical 64-Kbyte Block Erase Time
Program and Erase Suspend/Resume
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 12mA Active Read Current (Typical at 20MHz)
– 5µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)
– 9-ball UBGA (6 x 6 x 0.6 mm body - 1 mm pitch)
32-Mbit
2.7V Minimum
Serial Peripheral
Interface Serial
Flash Memory
AT25DF321A
3686F–DFLASH–1/2014

1 Page





AT25DF321A-MH-T pdf, ピン配列
AT25DF321A
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol
CS
SCK
SI (SIO)
SO (SOI)
WP
HOLD
VCC
GND
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will
be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin
will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is
required to end an operation. When ending an internally self-timed operation such as a program or erase
cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always latched in
on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of
SCK.
SERIAL INPUT (SERIAL INPUT/OUTPUT): The SI pin is used to shift data into the device. The SI
pin is used for all data input including command and address sequences. Data on the SI pin is always
latched in on the rising edge of SCK.
With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow two bits of
data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To maintain consistency
with SPI nomenclature, the SIO pin will be referenced as SI throughout the document with exception to
sections dealing with the Dual-Output Read Array command in which it will be referenced as SIO.
Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).
SERIAL OUTPUT (SERIAL OUTPUT/INPUT): The SO pin is used to shift data out from the device.
Data on the SO pin is always clocked out on the falling edge of SCK.
With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI) to allow two
bits of data (on the SOI and SI pins) to be clocked in on every rising edge of SCK. To maintain
consistency with SPI nomenclature, the SOI pin will be referenced as SO throughout the document with
exception to sections dealing with the Dual-Input Byte/Page Program command in which it will be
referenced as SOI.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted).
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to
“Protection Commands and Features” on page 18 for more details on protection features and the WP
pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not
be used. However, it is recommended that the WP pin also be externally connected to VCC whenever
possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin
will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to
start. A Hold condition pauses serial communication only and does not have an effect on internally self-
timed operations such as a program or erase cycle. Please refer to “Hold” on page 40 for additional
details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
GROUND: The ground reference for the power supply. GND should be connected to the system ground.
Asserted
State
Low
-
-
-
Low
Low
-
-
Type
Input
Input
Input/Output
Output/Input
Input
Input
Power
Power
3686F–DFLASH–1/2014
3


3Pages


AT25DF321A-MH-T 電子部品, 半導体
5. Device Operation
The AT25DF321A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25DF321A via the SPI bus which is comprised of four signal lines: Chip
Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The AT25DF321A features a dual-input program mode in which the SO pin becomes an input. Similarly, the device also
features a dual-output read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page Program command
description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the Dual-Output Read Array command,
the SI pin will be referenced as the SIO (Serial Input/Output) pin.
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK
polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF321A supports the two
most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal
when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI Modes 0 and 3,
data is always latched in on the rising edge of SCK and always output on the falling edge of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the
host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and data
bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25DF321A will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then
reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device, then
no operation will be performed and the device will simply return to the idle state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0. Since the
upper address limit of the AT25DF321A memory array is 3FFFFFh, address bits A23-A22 are always ignored by the device.
6 AT25DF321A
3686F–DFLASH–1/2014

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ AT25DF321A-MH-T データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
AT25DF321A-MH-T

32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory

Adesto
Adesto
AT25DF321A-MH-Y

32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory

Adesto
Adesto


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap