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HCPL-0710 の電気的特性と機能

HCPL-0710のメーカーはAgilent(Hewlett-Packard)です、この部品の機能は「40 ns Prop. Delay/ SO-8 Optocoupler」です。


製品の詳細 ( Datasheet PDF )

部品番号 HCPL-0710
部品説明 40 ns Prop. Delay/ SO-8 Optocoupler
メーカ Agilent(Hewlett-Packard)
ロゴ Agilent(Hewlett-Packard) ロゴ 




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HCPL-0710 Datasheet, HCPL-0710 PDF,ピン配置, 機能
H
40 ns Prop. Delay,
SO-8 Optocoupler
Technical Data
HCPL-0710
Features
• +5 V CMOS Compatibility
• 8 ns max. Pulse Width
Distortion
• 20 ns max. Prop. Delay Skew
• High Speed: 12 Mbd
• 40 ns max. Prop. Delay
• 10 kV/µs Minimum Common
Mode Rejection
• 0°C to 85°C Temp. Range
• Safety and Regulatory
Approvals
UL Recognized
2500 V rms for 1 min. per
UL 1577
CSA Component Acceptance
Notice #5
Description
Available in the SO-8 package
style, the HCPL-0710 optocoupler
utilizes the latest CMOS IC
technology to achieve outstanding
performance with very low power
consumption. The HCPL-0710
requires only two bypass
capacitors for complete CMOS
compatability.
Basic building blocks of the
HCPL-0710 are a CMOS LED
driver IC, a high speed LED and a
CMOS detector IC. A CMOS logic
input signal controls the LED
driver IC which supplies current
to the LED. The detector IC
incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
Functional Diagram
**VDD1 1
8 VDD2**
Applications
• Digital Fieldbus Isolation:
DeviceNet, SDS, Profibus
• AC Plasma Display Panel
Level Shifting
• Multiplexed Data
Transmission
• Computer Peripheral
Interface
• Microprocessor System
Interface
VI 2
*3
GND1 4
LED1
SHIELD
7 NC*
IO
6 VO
5 GND2
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
*Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally. External connections to pin 7 are not recommended.
**A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component
to prevent damage and/or degradation which may be induced by ESD.

1 Page





HCPL-0710 pdf, ピン配列
Regulatory Information
The HCPL-0710 has been
approved by the following
organizations:
UL
Recognized under UL 1577,
component recognition program,
File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
Insulation and Safety Related Specifications
Parameter
Symbol Value Units
Minimum External Air Gap
L(I01) 4.9 mm
(Clearance)
Minimum External Tracking L(I02) 4.8 mm
(Creepage)
Minimum Internal Plastic Gap
(Internal Clearance)
0.08 mm
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
CTI
200 Volts
IIIa
Conditions
Measured from input terminals to output
terminals, shortest distance through air.
Measured from input terminals to output
terminals, shortest distance path along body.
Insulation thickness between emitter and
detector; also known as distance through
insulation.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter
Storage Temperature
Ambient Operating Temperature[1]
Supply Voltages
Input Voltage
Output Voltage
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
Min.
Max.
Units Figure
TS -55
125 °C
TA
-40
+100
°C
VDD1, VDD2
0
5.5 Volts
VI
-0.5
VDD1 +0.5
Volts
VO
-0.5
VDD2 +0.5
Volts
IO 10 mA
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Symbol
Ambient Operating Temperature
Supply Voltages
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
TA
VDD1, VDD2
VIH
VIL
tr, tf
Min.
0
4.5
0.8 * VDD1
0.0
Max.
+85
5.5
VDD1
0.8
1.0
Units
°C
V
V
V
ms
Figure
1, 2


3Pages


HCPL-0710 電子部品, 半導体
4
3
2
1
0
0 20 40 60 80
TA (C)
Figure 4. Typical Pulse Width
Distortion vs. Temperature.
15
14
13
12
0 20 40 60 80
TA (C)
Figure 5. Typical Rise Time vs.
Temperature.
7
6
5
4
3
2
0 20 40 60 80
TA (C)
Figure 6. Typical Fall Time vs.
Temperature.
29
27
25
23 TPLH
21
TPHL
19
17
15
0 5 10 15 20 25 30 35
CI (pF)
Figure 7. Typical Propagation Delays
vs. Output Load Capacitance.
6
5
4
3
2
1
0
0 5 10 15 20 25 30 35
CI (pF)
Figure 8. Typical Pulse Width
Distortion vs. Output Load
Capacitance.
25
23
21
19
17
15
13
11
9
7
5
0 5 10 15 20 25 30 35
CI (pF)
Figure 9. Typical Rise Time vs. Load
Capacitance.
10
9
8
7
6
5
4
3
2
1
0
0 5 10 15 20 25 30 35
CI (pF)
Figure 10. Typical Fall Time vs. Load
Capacitance.

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
HCPL-0710

40 ns Prop. Delay/ SO-8 Optocoupler

Agilent(Hewlett-Packard)
Agilent(Hewlett-Packard)
HCPL-0710

40 ns Prop. Delay/ SO-8 Optocoupler

ETC
ETC
HCPL-0710

40 ns Propagation Delay / CMOS Optocoupler

Avago
Avago
HCPL-0710500

40 ns Prop. Delay/ SO-8 Optocoupler

Agilent(Hewlett-Packard)
Agilent(Hewlett-Packard)


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