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CD4027BCMのメーカーはFairchild Semiconductorです、この部品の機能は「Dual J-K Master/Slave Flip-Flop」です。 |
部品番号 | CD4027BCM |
| |
部品説明 | Dual J-K Master/Slave Flip-Flop | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとCD4027BCMダウンロード(pdfファイル)リンクがあります。 Total 6 pages
October 1987
Revised January 1999
CD4027BC
Dual J-K Master/Slave Flip-Flop with Set and Reset
General Description
The CD4027BC dual J-K flip-flops are monolithic comple-
mentary MOS (CMOS) integrated circuits constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent J, K, set, reset, and clock inputs
and buffered Q and Q outputs. These flip-flops are edge
sensitive to the clock input and change state on the posi-
tive-going transition of the clock pulses. Set or reset is
independent of the clock and is accomplished by a high
level on the respective input.
All inputs are protected against damage due to static dis-
charge by diode clamps to VDD and VSS.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s Low power: 50 nW (typ.)
s Medium speed operation: 12 MHz (typ.) with 10V
supply
Ordering Code:
Order Number Package Number
Package Description
CD4027BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4027BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP and SOIC
Top View
Inputs tn−1
(Note 1)
Outputs tn
(Note 2)
CL J K S R Q Q
Q
(Note 3)
I XOOO I
O
XOOO I I
O
OXOOO O
I
X I OO I O
I
XXOOX
(No Change)
X XX I OX I
O
X XXO I X O
I
X XX I I X I
I
I = HIGH Level
O = LOW Level
X = Don't Care
= LOW-to-HIGH
= HIGH-to-LOW
Note 1: tn−1 refers to the time interval prior to the positive clock pulse
transition
Note 2: tn refers to the time intervals after the positive clock pulse
transition
Note 3: Level Change
© 1999 Fairchild Semiconductor Corporation DS005958.prf
www.fairchildsemi.com
1 Page Absolute Maximum Ratings(Note 4)
(Note 5)
DC Supply Voltage (VDD)
−0.5 VDC to +18 VDC
Input Voltage (VIN)
−0.5V to VDD +0.5 VDC
Storage Temperature Range (TS)
−65°C to +150°C
Power Dissipation (PD)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)
260°C
Recommended Operating
Conditions (Note 5)
DC Supply Voltage (VDD)
3V to 15 VDC
Input Voltage (VIN)
0V to VDD VDC
Operating Temperature Range (TA)
−40°C to +85°C
Note 4: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device operation.
Note 5: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 6)
Symbol
Parameter
Conditions
IDD Quiescent Device Current VDD = 5V, VIN = VDD or VSS
VDD = 10V, VIN = VDD or VSS
VDD = 15V, VIN = VDD or VSS
VOL LOW Level
|IO| < 1 µA
Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VOH HIGH Level
|IO| < 1 µA
Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VIL LOW Level
VDD = 5V, VO = 0.5V or 4.5V
Input Voltage
VDD = 10V, VO = 1V or 9V
VDD = 15V, VO = 1.5V or 13.5V
VIH HIGH Level
VDD = 5V, VO = 0.5V or 4.5V
Input Voltage
VDD = 10V, VO = 1V or 9V
VDD = 15V, VO = 1.5V or 13.5V
IOL LOW Level Output
VDD = 5V, VO = 0.4V
Current (Note 7)
VDD = 10V, VO = 0.5V
VDD = 15V, VO = 1.5V
IOH HIGH Level Output
VDD = 5V, VO = 4.6V
Current (Note 7)
VDD = 10V, VO = 9.5V
VDD = 15V, VO = 13.5V
IIN Input Current
VDD = 15V, VIN = 0V
VDD = 15V, VIN = 15V
Note 6: VSS = 0V unless otherwise specified.
Note 7: IOH and IOL are tested one output at a time.
−40°C
Min Max
4
8
16
+25°C
Min Typ Max
4
8
16
+85°C
Min Max
30
60
120
Units
µA
µA
µA
0.05
0.05
0.05
0 0.05
0 0.05
0 0.05
0.05 V
0.05 V
0.05 V
4.95
9.95
14.95
3.5
7.0
11.0
0.52
1.3
3.6
−0.52
−1.3
−3.6
1.5
3.0
4.0
−0.3
0.3
4.95
9.95
14.95
3.5
7.0
11.0
0.44
1.1
3.0
−0.44
−1.1
−3.0
5
10
15
0.88
2.25
8.8
−0.88
−2.25
−8.8
−10−5
10−5
1.5
3.0
4.0
−0.3
0.3
4.95
9.95
14.95
3.5
7.0
11.0
0.36
0.9
2.4
−0.36
−0.9
−2.4
1.5
3.0
4.0
−1.0
1.0
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
µA
µA
3 www.fairchildsemi.com
3Pages Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assumeany responsibility for use of any circuitry described, no circuit patent licenses are impliedandFairchildreserves theright at any timewithout noticetochange saidcircuitry andspecifications.
6 Page | |||
ページ | 合計 : 6 ページ | ||
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部品番号 | 部品説明 | メーカ |
CD4027BC | Dual J-K Master/Slave Flip-Flop with Set and Reset | National Semiconductor |
CD4027BC | Dual J-K Master/Slave Flip-Flop | Fairchild Semiconductor |
CD4027BCM | Dual J-K Master/Slave Flip-Flop | Fairchild Semiconductor |
CD4027BCN | Dual J-K Master/Slave Flip-Flop | Fairchild Semiconductor |