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GW3887AIK の電気的特性と機能

GW3887AIKのメーカーはConexantです、この部品の機能は「Wireless LAN Integrated Medium Access Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 GW3887AIK
部品説明 Wireless LAN Integrated Medium Access Controller
メーカ Conexant
ロゴ Conexant ロゴ 




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GW3887AIK Datasheet, GW3887AIK PDF,ピン配置, 機能
GW3887A
Wireless LAN Integrated Medium Access Controller with
Baseband Processor
The Conexant GW3887A Wireless LAN Integrated Media Access Controller
with Baseband Processor is part of both the PRISM GT™ single band and
PRISM WWR™ dual band radio chip sets. The GW3887A directly interfaces
with Conexant’s ISL3686B Single Band Direct Conversion Transceiver.
Adding Conexant’s ISL3084 5GHz VCO and ISL3980 Power Amp completes
an end-to-end WLAN chip set solution compliant with 802.11b/g standards.
Additionally, the GW3887A directly interfaces with Conexant’s ISL3692 Dual
Band Direct Conversion Transceiver. Adding Conexant’s ISL3092 11GHz
VCO and ISL3992 Dual Band Power Amp completes an end-to-end WLAN
chip set solution compliant with 802.11a/b/g/h/i/j standards. The 802.11
protocol is implemented in firmware supporting custom WLAN solutions.
The GW3887A improvements over the GW3887 include the addition of an
internal 48MHz oscillator, which eliminates several external components
from the radio design.
Software implements the full IEEE 802.11 Wireless LAN MAC protocol. It
supports BSS and IBSS operation under DCF, and operation under the
optional Point Coordination Function (PCF). Active scanning is performed
autonomously once initiated by host command. Host interface command
and status handshakes allow concurrent operations from multi-threaded I/
O drivers.
Orthogonal Frequency Division Multiplexing (OFDM) of 52 sub-carriers
modulated with BPSK, QPSK, 16QAM or 64QAM and a variety of
convolutional coding rates provides 8 selectable data rates at 2.4GHz and
5GHz. Differential phase shift keying modulation schemes, DBPSK and
DQPSK with data scrambling capability along with Complementary Code
Keying provide an additional 4 selectable data rates at 2.4GHz.
Built-in flexibility allows the GW3887A to be configured for a range of
applications. The MAC is based on the ARM 946E processor core that
offers a wide variety of code development support tools.
The GW3887A is housed in a thin plastic BGA package suitable for USB
2.0 Wireless LAN small form factor circuit card applications.
Features
• Firmware implements the full IEEE
802.11a/b/g/h/i/j Wireless LAN MAC
protocols
• Internal WEP Engine allows 64 or 128 bit
Encryption
• AES Hardware Accelerator
• Start-up modes allow the USB vendor and
device ID to be initialized from a small
external serial EEPROM. This allows
firmware to be downloaded from the host.
• On-chip SRAM memory
• A low frequency crystal oscillator can
maintain time, which allows the high
frequency clock source to be powered off
during sleep mode.
• Firmware controlled antenna diversity
• Data Rates: 1, 2, 5.5, 6, 9, 11, 12, 18, 24,
36, 48, & 54Mbps
• Modulation: OFDM with BPSK, QPSK,
16QAM, 64QAM; DBPSK; DQPSK and
CCK
• Convolutional coding and interleaving on
all OFDM rates
• Targeted for OFDM Multipath Delay
Spreads >800ns for 6Mbps, and >100ns
for 54Mbps
• Targeted for CCK Multipath Delay
Spreads >90ns at 11Mbps, >200ns at
5.5Mbps and >360ns at 1 and 2Mbps
• Direct interface with the ISL3692 and
ISL3686 Direct Conversion transceiver
• USB 2.0 Wireless LAN Adapters
A/D
BB
PROCESSOR
MAC
USB
2.0
Interface
D/A
GW3887A
SRAM
Figure 1: Simplified Block Diagram
Preliminary Data Sheet
November 12, 2004
Conexant Systems, Inc.
Proprietary - Use Pursuant to NDA
DO-406971-DS
Issue 2

1 Page





GW3887AIK pdf, ピン配列
November 12, 2004
GW3887A Data Sheet
Table 1: GW3887A Signal Descriptions (Sheet 2 of 5)
Pin Name
RESETn
GNDD
TMSEL3
TMSEL0
GNDD
IoVDDD
TEST7
TEST5
coreVDDD
UTMI-0
OSCENABLE
GNDD
coreVDDD
GP2-12
GP2-9
SERDOUT
UTMI-3
TRSTn
TCK
TEST11
TEST8
coreVDDD
GNDD
ioVDDD
LNA_H/L
CLKIN40
GP1-3
GP1-2
FAA_HRDn
ioVDDD
ANALOG_TEST
VSSA33C
VSSDPHY
VDDDPHY
GP2-4
GP2-7
GP1-15
coreVDDD
NC
VDDA33C
XI
XO
GP2-6
GP2-8
GNDD
GP2-2
BGA Ball
Assignment
c5
c6
c7
c8
c9
d1
d10
d11
d12
d13
d14
d15
d16
d2
d3
d4
d5
d6
d7
d8
d9
e1
e13
e14
e15
e16
e2
e3
e4
f1
f13
f14
f15
f16
f2
f3
f4
g1
g13
g14
g15
g16
g2
g3
g4
h1
Pad Type
Schmitt input
supply
Bidir as input
Bidir as input
supply
supply
Bidir as output
Bidir as output
supply
input
Bidir as output
supply
supply
bidir
Bidir
Output
Output
Bidir as input
Bidir as input
Bidir as output
Bidir as output
supply
supply
supply
Bidir as output
Schmitt input
bidir
bidir
Schmitt
supply
Input/Output
supply
supply
supply
bidir
bidir
bidir
supply
none
supply
analog
analog
bidir
bidir
supply
bidir
Pin I/O
TYPE
up
none
down
down
none
none
none
none
none
none
none
none
none
up
up
none
none
up
up
none
none
none
none
none
none
none
down
down
up
none
-
-
none
none
down
down
up
none
none
-
-
-
down
up
none
down
Description
Active low reset for chip
Digital IO and core ground
Testmode select pin
Testmode select pin
Digital IO and core ground
Digital IO supply (3.3V)
BBP testbus
BBP testbus
Digital core supply(1.8V)
UTMI_CLK
Canned oscillator enable signal, high is active
Digital IO and core ground
Digital core supply(1.8V)
Multi-ICE RTCK
LED1 Activity LED (and Uart BaudOut_N)
Serial host data out for 4-wire interface
UTMI_TxValid
JTAG test reset
JTAG test clock
BBP testbus (MSB)
BBP testbus
Digital core supply(1.8V)
Digital IO and core ground
Digital IO supply (3.3V)
AGC 30dB pad signal
High frequency (40MHz) crystal pad cell
PA_PE5G 5GHz PA enable
USB_VBUS
Hardware input for FAA switch
Digital IO supply (3.3V)
Voltage used in conjuction with ATE testing
USB2.0 Common Analog ground
Gnd for Digital portion of USB Phy
1.8V supply for Digital portion of USB Phy
Uart DTR_N
Uart CTS_N
FAAmode_n
Digital core supply(1.8V)
No connect, no pad
USB2.0 Common Analog supply
48-Mhz Crystal or clock input if external clock used
48-Mhz Crystal output. Unused unless using external crystal
Uart RTS_N
Uart DCD_N
Digital IO and core ground
FAA LED (LED2)
DO-406971-DS
Issue 2
Conexant Systems, Inc.
Proprietary - Use Pursuant to NDA
3


3Pages


GW3887AIK 電子部品, 半導体
GW3887A Data Sheet
Table 1: GW3887A Signal Descriptions (Sheet 5 of 5)
Pin Name
TX_IFagc
GNDD1
NC
GNDD0
Qoout_P
Qoout_N
Ioout_P
Ioout_N
Iin_P
Qin_N
Iout_N
BGA Ball
Assignment
t14
t15
t16
t2
t3
t4
t5
t6
t7
t8
t9
Pad Type
analog
analog
none
analog
analog
analog
analog
analog
analog
analog
analog
Pin I/O
TYPE
none
none
none
none
none
none
none
none
none
none
none
Description
Iout for Tx AGC DAC
Digital ground for DACs other than offset
No connect, no pad
Offset DACs digital ground
Iout+ for Q offset DAC (QOFFSET+)
Iout- for Q offset DAC (QOFFSET-)
Iout+ for I offset DAC (IOFFSET+)
Iout- for I offset DAC (IOFFSET-)
Input signal + for I Rx ADC (RXI+)
Input signal for Q Rx ADC (RXQ-)
Iout- for I Tx DAC (TXI-)
2 Thermal Information
Thermal resistance information is provided in Table 2.
November 12, 2004
Table 2: Thermal Resistancea
Product
θJA (oC/W)
BGA Package
42
a. θJA is measured with the component mounted on high effective
thermal conductivity test board in free air. Refer to DO-406099-TC
Technical Brief(TB379) - Thermal Characterization of Packaged
Semiconductor Devices for details.
Maximum Storage Temperature Range . . . . . . . -65°C to 150°C
Maximum Junction Temperature . . . . . . . . . . . . 125°C
NOTE:
For recommended soldering conditions refer to DO-405727-TC Technical Brief (TB334) - Guidelines for
Soldering Surface Mount Components to PC Boards.
Conexant Systems, Inc.
DO-406971-DS
6
Proprietary - Use Pursuant to NDA
Issue 2

6 Page



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共有リンク

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