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HCPL2601M PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 HCPL2601M
部品説明 Single-Channel High-Speed 10 MBit/s Logic Gate Optocouplers
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 



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HCPL2601M Datasheet, HCPL2601M PDF,ピン配置, 機能
April 2013
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M
High-Speed 10 MBit/s Logic Gate Optocouplers
Features
Very High Speed – 10 MBit/s
Superior CMR – 10 kV/µs
Fan-out of 8 Over -40°C to +85°C
Logic Gate Output
Strobable Output
Wired OR-open Collector
U.L. Recognized (File # E90700, Vol. 2)
Applications
Ground Loop Elimination
LSTTL to TTL, LSTTL or 5 V CMOS
Line Receiver, Data Transmission
Data Multiplexing
Switching Power Supplies
Pulse Transformer Replacement
Computer-peripheral Interface
Description
The 6N137M, HCPL2601M, HCPL2611M single-channel
and HCPL2630M, HCPL2631M dual-channel optocou-
plers consist of a 850 nm AlGaAS LED, optically coupled
to a very high speed integrated photo-detector logic gate
with a strobable output. This output features an open col-
lector, thereby permitting wired OR outputs. The
switching parameters are guaranteed over the tempera-
ture range of -40°C to +85°C. A maximum input signal of
5 mA will provide a minimum output sink current of
13 mA (fan out of 8).
An internal noise shield provides superior common
mode rejection of typically 10 kV/µs. The HCPL2601M
and HCPL2631M has a minimum CMR of 5 kV/µs. The
HCPL2611M has a minimum CMR of 10 kV/µs.
Schematics
Package Outlines
N/C 1
+2
V
F
_3
N/C 4
8
V
CC
7V
E
+1
V
F1
_2
6V
O
5 GND
_3
V
F2
+4
8
V
CC
7V
01
6V
02
5 GND
6N137M
HCPL2601M
HCPL2611M
HCPL2630M
HCPL2631M
(Preliminary)
A 0.1µF bypass capacitor must be connected between pins 8 and 5(1).
Figure 1. Schematics
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8
8
1
8
1
8
8
1
1
Figure 2. Package Options
Truth Table (Positive Logic)
Input
Enable
HH
LH
HL
LL
H NC
L NC
Output
L
H
H
H
L
H
www.fairchildsemi.com

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