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PDF HD74LV595A Data sheet ( Hoja de datos )

Número de pieza HD74LV595A
Descripción 8-bit Shift Registers with 3-state Outputs
Fabricantes Hitachi Semiconductor 
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HD74LV595A
8-bit Shift Registers with 3-state Outputs
ADE-205-281 (Z)
1st Edition
April 1999
Description
This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register anf the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register anf the storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register state will always be one clock pulse ahead of the storage
register. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)

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HD74LV595A pdf
Recommended Operating Conditions
Item
Symbol Min
Max
Supply voltage range
Input voltage range
Output voltage range
VCC 2.0
VI 0
VO 0
0
5.5
5.5
VCC
5.5
Output current
IOH
–50
–2
— –6
— –12
IOL
50
2
—6
— 12
Input transition rise or fall rate t /v
0
200
0 100
0 20
Operating free-air temperature Ta
–40 85
Note: Unused or floating inputs must be held high or low.
HD74LV595A
Unit
V
V
V
µA
mA
µA
mA
ns/V
°C
Conditions
H or L
High impedance state
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
5

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HD74LV595A arduino
HD74LV595A
Switching Characteristics (cont)
VCC = 5.0 ± 0.5 V
Ta = 25°C
Item
Symbol Min Typ
Maximum
clock
frequency
fmax
135 185
95 155
Propagation
delay time
tPLH/tPHL
6.2
7.7
— 5.4
— 6.9
tPHL — 5.9
— 7.4
Enable time
Disable time
Setup time
tZH
tZL
tHZ
tLZ
tSU
— 4.8
— 8.3
— 4.8
— 7.6
3.0 —
5.0 —
5.0 —
2.5 —
Hold time
th
Pulse width tw
2.0 —
0.0 —
0.0 —
5.0 —
5.0 —
5.0 —
Ta = –40 to 85°C
Max Min Max
Test
FROM
Unit Conditions (Input)
— 115 —
— 85
MHz
CL = 15 pF
CL = 50 pF
TO
(Output)
8.2 1.0
10.2 1.0
7.4 1.0
9.4 1.0
8.0 1.0
10.0 1.0
8.6 1.0
10.6 1.0
8.6 1.0
11.0 1.0
— 3.0
— 5.0
— 5.0
— 2.5
— 2.0
— 0.0
— 0.0
— 5.0
— 5.0
— 5.0
9.4
11.4
8.5
10.5
9.1
11.1
10.0
12.0
10.0
11.0
ns CL = 15 pF SRCLK
QH'
CL = 50 pF
CL = 15 pF RCLK
QA – QH
CL = 50 pF
CL = 15 pF SRCLK
QH'
CL = 50 pF
ns CL = 15 pF G
QA – QH
CL = 50 pF
ns CL = 15 pF
CL = 50 pF
ns SER before SRCLK
SRCLK before RCLK
SRCLR low before RCLK
SRCLR high (inactive)
before SRCLK
ns SER after SRCLK
SRCLK after RCLK
SRCLR low after RCLK
ns RCLK high or low
SRCLK high or low
SRCLR low
11

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