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HD74LV573A の電気的特性と機能

HD74LV573AのメーカーはHitachi Semiconductorです、この部品の機能は「Octal D-type Transparent Latches with 3-state Outputs」です。


製品の詳細 ( Datasheet PDF )

部品番号 HD74LV573A
部品説明 Octal D-type Transparent Latches with 3-state Outputs
メーカ Hitachi Semiconductor
ロゴ Hitachi Semiconductor ロゴ 




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HD74LV573A Datasheet, HD74LV573A PDF,ピン配置, 機能
HD74LV573A
Octal D-type Transparent Latches with 3-state Outputs
ADE-205-279A (Z)
2nd Edition
July 1999
Description
The HD74LV573A has eight D-type latches with three-state outputs in a 20-pin package. When the latch
enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D
inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is
suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption
extends the battery life.
Features
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)
Function Table
Inputs
OE LE
D
Output Q
L HHH
L HL L
L L X Q0
HXXZ
Note: H: High level
L: Low level
X: Immaterial
Z: High impedance
Q0: Output level before the indicated steady state input conditions were established

1 Page





HD74LV573A pdf, ピン配列
HD74LV573A
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
VCC
VI
VO
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air)*3
I IK
I OK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±35
±70
V
V
V
mA
mA
mA
mA
835 mW
Output: H or L
VCC: Z or VCC: OFF
VI < 0
VO < 0 or VO > VCC
VO = 0 to VCC
SOP
757 TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
3


3Pages


HD74LV573A 電子部品, 半導体
HD74LV573A
Switching Characteristics
VCC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
Item
Propa-
gation
delay
time
Enable
time
Disable
time
Setup
time
Hold
time
Pulse
width
Symbol Min Typ
tPLH — 8.9
tPHL
— 9.6
— 10.9
— 11.6
tZH — 9.3
tZL
— 11.4
tHZ — 6.7
tLZ
— 8.6
tsu 5.0 —
th 2.0 —
tw 6.5 —
Max
15.8
16.2
18.7
19.1
16.2
19.0
12.6
17.3
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.0
2.0
6.5
Max
18.0
19.0
21.0
23.0
19.0
22.0
15.0
19.0
Unit
ns
Test Conditions
CL = 15 pF
CL = 50 pF
ns CL = 15 pF
CL = 50 pF
ns CL = 15 pF
CL = 50 pF
ns
ns
ns
FROM
(Input)
D
TO
(Output)
Q
LE
D
LE
OE Q
OE Q
Data before LE
Data after LE
LE “H”
6

6 Page



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部品番号部品説明メーカ
HD74LV573A

Octal D-type Transparent Latches with 3-state Outputs

Hitachi Semiconductor
Hitachi Semiconductor


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