PDF HD74HCT74A Data sheet ( Hoja de datos )

Número de pieza	HD74HCT74A
Descripción	Dual D-type Positive Edge-triggered Flip Flops with Clear and Preset
Fabricantes	Hitachi Semiconductor
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No Preview Available ! HD74HCT74A Dual D–type Positive Edge–triggered Flip Flops with Clear and Preset ADE-205-290 (Z) 1st. Edition June 1999 Description The HD74HCT74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Features • VCC = 4.5 to 5.5 V operation • Input terminal has protection diode Function Table Inputs Outputs PRE CLR CLK D Q Q L HX XHL HL X XL H L L X X H 1 H 1 HH↑ HHL HH↑ L L H HHL X Q0 Q0 H : High level L : Low level X : Immaterial ↑ : Low to high transition Q0 : Level to Q before the indicated steady state input conditions were established. Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and clear go high simultaneously. 1 page HD74HCT74A Switching Characteristics (CL = 50 pF) Item Symbol VCC (V) Maximum clock frequency Propagation delay time f max t PLH t PHL Output rise / fall time Setup time tr / tf t su Hold time th Pulse width tw Input capacitance CI Power dissipation CPD capacitance 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 — — Ta = 25°C Min Typ 27 78 30 92 — 14 — 12 — 14 — 13 —7 —6 10 — 9— 5— 5— 0— 0— 15 — 14 — —3 — 35 Max — — 28 25 22 20 15 13 — — — — — — — — 10 — Ta = –40 to 85°C Unit Input Output Min Max FROM TO 22 — MHz 24 — — 35 ns PRE, Q, Q — 32 CLR — 28 CLK Q, Q — 25 — 19 ns Each — 16 output 13 — ns D 12 — 5— PRE, CLR 5— inactive 0 — ns 0— 19 — ns 17 — — 10 pF — — pF 5 5 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HD74HCT74A	Dual D-type Positive Edge-triggered Flip Flops with Clear and Preset	Hitachi Semiconductor

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