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PDF HD74HCT137 Data sheet ( Hoja de datos )

Número de pieza HD74HCT137
Descripción 3-to-8-line Decoder/Demultiplexer with Address Latch
Fabricantes Hitachi Semiconductor　
Logotipo Hitachi Semiconductor Logotipo



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No Preview Available ! HD74HCT137 Hoja de datos, Descripción, Manual

HD74HCT137
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs.
When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the
latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1
and G2, control the state of the outputs independently of the select or latch-enable inputs.
All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the
implementation of glitchfree decoders in stored-address applications in bus oriented systems.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

1 page




HD74HCT137 pdf
19.20
20.00 Max
16
9
1
1.3
1.11 Max
8
Unit: mm
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25
+
–
0.13
0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-16
Conforms
Conforms
1.07 g

5 Page










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