(PDF) HD74HC4024 Datasheet - 7-stage Binary Counter

Número de pieza	HD74HC4024
Descripción	7-stage Binary Counter
Fabricantes	Hitachi Semiconductor
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No Preview Available ! HD74HC4024 7-stage Binary Counter Description The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Features • High Speed Operation: tpd (Clock to Q1) = 14 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Clock L L H H Reset L H L H L H L H Outputs State No change All outputs are low No change All outputs are low No change All outputs are low Advance to next state All outputs are low 1 page 19.20 20.32 Max 14 8 1 1.30 7 2.39 Max Unit: mm 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 + – 0.10 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g 5 Page

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PDF HD74HC4024 Data sheet ( Hoja de datos )