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28C512 の電気的特性と機能

28C512のメーカーはON Semiconductorです、この部品の機能は「CAT28C512」です。


製品の詳細 ( Datasheet PDF )

部品番号 28C512
部品説明 CAT28C512
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




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28C512 Datasheet, 28C512 PDF,ピン配置, 機能
CAT28C512/513
512K-Bit CMOS PARALLEL EEPROM
FEATURES
s Fast Read Access Times: 120/150 ns
s Low Power CMOS Dissipation:
–Active: 50 mA Max.
–Standby: 200 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–5ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel EEPROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
BLOCK DIAGRAM
s Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC and TSOP packages.
A7A15
VCC
CE
OE
WE
A0A6
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
65,536 x 8
EEPROM
ARRAY
128 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0I/O7
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1007, Rev. I

1 Page





28C512 pdf, ピン配列
CAT28C512/513
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55°C to +125°C
Storage Temperature ....................... 65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... 2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
*COMMENT
Stresses above those listed under Absolute Maximum
Ratingsmay cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min
100,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol
ICC
Parameter
VCC Current (Operating, TTL)
Min Typ
Max.
50
Units
mA
Test Conditions
CE = OE = VIL, f=6MHz
All I/Os Open
ICCC(5)
VCC Current (Operating, CMOS)
25 mA CE = OE = VILC, f=6MHz
All I/Os Open
ISB
ISBC(6)
VCC Current (Standby, TTL)
VCC Current (Standby, CMOS)
3 mA CE = VIH, All I/Os Open
200 µA CE = VIHC,
All I/Os Open
ILI Input Leakage Current
-10
10 µA VIN = GND to VCC
ILO Output Leakage Current
-10
10 µA VOUT = GND to VCC,
CE = VIH
VIH(6)
High Level Input Voltage
2
VCC +0.3 V
VIL(5)
Low Level Input Voltage
-1
0.8 V
VOH High Level Output Voltage
2.4
V IOH = 400µA
VOL Low Level Output Voltage
0.4 V IOL = 2.1mA
VWI Write Inhibit Voltage
3.5
V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC +1V.
(5) VILC = 0.3V to +0.3V.
(6) VIHC = VCC 0.3V to VCC +0.3V.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1007, Rev . I


3Pages


28C512 電子部品, 半導体
CAT28C512/513
DEVICE OPERATION
Read
Data stored in the CAT28C512/513 is transferred to the
data bus when WE is held high, and both OE and CE
are held low. The data bus is set to a high impedance
state when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
ADDRESS
CE
OE
WE
DATA OUT
tRC
tCE
tOE
VIH
tLZ
HIGH-Z
tOLZ
tOH
DATA VALID
tAA
tOHZ
tHZ
DATA VALID
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
tAS tAH
tCS
tCH
OE
WE
DATA OUT
DATA IN
Doc. No. MD-1007, Rev. I
tOES
tWP
HIGH-Z
tOEH
tBLC
DATA VALID
tDS
tDH
6
tWC
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice

6 Page



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部品番号部品説明メーカ
28C512

CAT28C512

ON Semiconductor
ON Semiconductor


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