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PDF HD74HC165 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC165 | |
| Descripción | Parallel-load 8-bit Shift Register | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74HC165
Parallel-load 8-bit Shift Register
Description
This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are
enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary
output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with
the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of
the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the
parallel inputs is loaded directly into the register independent of the state of the clock.
Features
• High Speed Operation: tpd (Clock to QH) = 21 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Shift/Load
L
H
H
H
H
Clock Inhibit
X
L
L
L
H
Clock
X
L
X
Parallel
Serial A ······ H
X a ······h
XX
HX
LX
XX
Internal outputs
QA QB
ab
QA0
H
QB0
QAn
L QAn
QA0
QB0
Output
QH
h
QH0
QGn
QGn
QH0
1 page  
HD74HC165
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = 25°C
Ta = –40 to
+85°C
Item
Pulse width
Symbol
tw
VCC (V)
2.0
4.5
Min Typ Max Min
80 — — 100
16 6 — 20
Max Unit
— ns
—
6.0 14 — — 17 —
Output rise/fall
time
t TLH
t THL
2.0 — — 75 — 95 ns
4.5 — 5 15 — 19
6.0 — — 13 — 16
Input capacitance Cin — — 5 10 — 10 pF
Test Conditions
Clock, Shift/Load
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HD74HC165.PDF ] | |
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