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PDF ISL6622A Data sheet ( Hoja de datos )
| Número de pieza | ISL6622A | |
| Descripción | VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
VR11.1 Compatible Synchronous
Rectified Buck MOSFET Drivers
The ISL6622A is a high frequency MOSFET driver designed
to drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. The advanced
PWM protocol of ISL6622A is specifically designed to work
with Intersil VR11.1 controllers and combined with
N-Channel MOSFETs, form a complete core-voltage regulator
solution for advanced microprocessors. When ISL6622A
detects a PSI protocol sent by an Intersil VR11.1 controller, it
activates Diode Emulation (DE) operation; otherwise, it
operates in normal Continuous Conduction Mode (CCM)
PWM mode.
In the 8 Ld SOIC package, the ISL6622A drives the upper
gate to 12V while the lower get can be driven from 5V to 12V.
The 10 Ld DFN part allows for more flexibility. The upper gate
can be driven from 5V to 12V using the UVCC pin and the
lower gate can also be driven from 5V to 12V using the LVCC
pin. This provides the flexibility necessary to optimize
applications involving trade-offs between gate charge and
conduction losses.
To further enhance light load efficiency, the ISL6622A
enables diode emulation operation during PSI mode. This
allows Discontinuous Conduction Mode (DCM) by detecting
when the inductor current reaches zero and subsequently
turning off the low side MOSFET to prevent it from sinking
current.
An advanced adaptive shoot-through protection is integrated
to prevent both the upper and lower MOSFETs from
conducting simultaneously and to minimize dead time. The
ISL6622A has a 20kΩ integrated high-side gate-to-source
resistor to prevent self turn-on due to high input bus dV/dt.
This driver adds an overvoltage protection feature
operational while VCC is below its POR threshold; the
PHASE node is connected to the gate of the low side
MOSFET (LGATE) via a 10kΩ resistor limiting the output
voltage of the converter close to the gate threshold of the low
side MOSFET, dependent on the current being shunted,
which provides some protection to the load should the upper
MOSFET(s) become shorted.
ISL6622A
March 19, 2009
FN6601.2
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
• 36V Internal Bootstrap Schottky Diode
• Diode Emulation For Enhanced Light Load Efficiency
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Advanced PWM Protocol (Patent Pending) to Support PSI
Mode, Diode Emulation, Three-State Operation
• Pre-POR Overvoltage Protection for Start-up and
Shutdown
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Applications
• High Light Load Efficiency Voltage Regulators
• Core Regulators for Advanced Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck
Regulators” for Power Train Design, Layout Guidelines,
and Feedback Compensation Design
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6622A
Electrical Specifications
Recommended Operating Conditions. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Three-State Upper Gate Rising Threshold (Note 4)
VCC = 12V
- 3.2 -
V
Three-State Upper Gate Falling Threshold (Note 4)
VCC = 12V
- 2.8 -
V
UGATE Rise Time (Note 4)
tRU
VVCC = 12V, 3nF Load, 10% to 90%
-
26
-
LGATE Rise Time (Note 4)
tRL
VVCC = 12V, 3nF Load, 10% to 90%
-
18
-
UGATE Fall Time (Note 4)
tFU
VVCC = 12V, 3nF Load, 90% to 10%
-
18
-
LGATE Fall Time (Note 4)
tFL
VVCC = 12V, 3nF Load, 90% to 10%
-
12
-
UGATE Turn-On Propagation Delay (Note 4)
tPDHU VVCC = 12V, 3nF Load, Adaptive
- 20 -
LGATE Turn-On Propagation Delay (Note 4)
tPDHL VVCC = 12V, 3nF Load, Adaptive
- 10 -
UGATE Turn-Off Propagation Delay (Note 4)
tPDLU VVCC = 12V, 3nF Load
- 10 -
LGATE Turn-Off Propagation Delay (Note 4)
tPDLL
VVCC = 12V, 3nF Load
- 10 -
LG/UG Three-State Propagation Delay (Note 4)
tPDTS VVCC = 12V, 3nF Load
- 10 -
Diode Braking Holdoff Time (Note 4)
tUG_OFF_DB VVCC = 12V
- 60 -
Minimum LGATE On-Time at Diode Emulation
tLG_ON_DM VVCC = 12V
230 330 450
OUTPUT (Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
IU_SOURCE VVCC = 12V, 3nF Load
RU_SOURCE 20mA Source Current
IU_SINK VVCC = 12V, 3nF Load
RU_SINK 20mA Sink Current
IL_SOURCE VVCC = 12V, 3nF Load
RL_SOURCE 20mA Source Current
IL_SINK VVCC = 12V, 3nF Load
RL_SINK 20mA Sink Current
- 1.25 -
- 2-
- 2-
- 1.35 -
- 2-
- 1.35 -
- 3-
- 0.9 -
A
Ω
A
Ω
A
Ω
A
Ω
Functional Pin Descriptions
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
- 3 NC No Connect
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation;
see “Description” on page 6 for further details. Connect this pin to the PWM output of the controller.
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 LVCC This pin supplies power to the lower gate drive. Its operating range is +5V to +12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
- 8 UVCC This pin supplies power to the upper gate drive. Its operating range is +5V to +12V. Place a high quality low ESR
ceramic capacitor from this pin to GND.
7 9 VCC Connect this pin to 12V bias supply. This pin supplies power to the upper gate in the SOIC. Place a high quality
low ESR ceramic capacitor from this pin to GND.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
- 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5 FN6601.2
March 19, 2009
5 Page 
ISL6622A
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45°
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1
0.0040 0.0098 0.10
0.25
-
B
0.013 0.020 0.33
0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.1890 0.1968 4.80
5.00
3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC
1.27 BSC
-
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L
0.016 0.050 0.40
1.27
6
N8
87
α 0° 8° 0° 8° -
Rev. 1 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN6601.2
March 19, 2009
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL6622A.PDF ] | |
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